삼성의 VLSI CAD 기술

참고문헌

1. 전자공학회지 v.16 no.1 삼성의 VLSICAD시스템 공정택
2. BACUS An Automatic Gate CD Control for a Full Chip Scale SRAM Device C.H. Park;T.G. Kim;H.J. Lee;J.T. Kong;S.H.Lee
3. SSICT Automatic Optical Proximity Correction Using Aerial Image Simulation and Newton Optimization Scheme C.H. Park;Y.H. Kim;C.S. Yun;K.H. Kim;S.H. Lee
4. 97BACUs 3D Electron Beam Lithography Simulator V2.0 for the 1 Giga-bit Era Photomask Manufacturing Y.H. Kim;B.C. Ha;H.J. Lee;J.M. Sohn;J.T. Kong;S.H. Lee
5. 5th ICVC Electron Beam Lithography Simulation for the 1 Giga-bit DRAM Photomask Manufacturing Y.H. Kim;B.C. Cha;H.J. Lee;J.T. Kong;S.H. Lee
6. 5th ICVC Physically Based Three Dimensional Modeling of Ion Implantation for ULSI and GSI Device Technology Development and Manufacturing M.S. Son;H.J. Hwang;J.H. Lee;H.J. Lee;T.S. Park
7. SISPAD Elasto-Viscoplastic Modeling for Three-Dimensional Oxidation Process Simulation J.H. Lee;M.S. Son;C.S. Yun;K.H. Kim;H.J. Hwang
8. ECS Reactive Ion Etch Profile Simulation for a SiO2 Contact Hole with Photoresist Mask Erosion J.S. Park;H.J. Lee;K.H. Kim;S.H. Lee
9. SSICT RIE Process Limit Consideration Through Profile Simulation J.S. Park;H.J. Lee;K.H. Kim;S.H. Lee
10. SISPAD Modeling of Polymer Neck Generation and Its Effects on the Etch Profile in Oxide Contact Hole Etching Using Ar, CHF3, AND CF4 Gases J.S. Park;H.J. Lee;J.T. Kong;S.H. Lee
11. ECS Pad Deformation and CMP Profile Simulation for Shallow Trench Isolation Process Y.H. Kim;T.K. Kim;H.J. Lee;K.H. Kim;S.H. Lee
12. SISPAD CMP Profile Simulation Using an Elastic Model on Nonlinear Contact Analysis Y.H. Kim;T.K. Kim;H.J. Lee;J.T. Kong;S.H. Lee
13. AVS Three Dimensional Modeling of SiO2 CMP Based on Pad Deformation T.K. Kim;Y.H. Kim;H.J. Lee;J.T. Kong;S.H. Lee
14. ESREF Improving the ESD Performance of Input Protection Circuits in Retrograde Well and STI structures Y.K. Park;T.H. Kang;C.H. Choi;J.T. Kong;S.H. Lee
15. 5th ICVC The Capacitance and Resistance Effects on Charged Device Mode(CDM) ESD in High-Performance Memory Devices Y.K. Park;Y.K. Park;C.H. Choi;J.T. Kong;S.H. Lee
16. SISPAD An Integrated TCAD System for VLSI Reliability Simulation J.K. Park;T.S. Park;S.H. Lee;C.H. Choi;K.H. Kim
17. SISPAD A Realistic Methodology for the Worst Case Analysis of VLSI Circuit Performances S.H. Lee;K.H. Kim;J.K. Park;C.H. Choi;J.T. Kong;W.W. Lee;W.S. Lee;J.H. Yoo;S.I. Cho
18. ICCAD An Efficient Statistical Analysis Methodology and Its Application to High-Density DRAMs S.H. Lee;C.H. Choi;J.T. Kong;W.S. Lee;S.C. Hong
19. SISPAD A Characterization Tool for Current Degradation Effects of Abnormally Structured MOS Transistors J.K. Park;C.H. Choi;Y.K. Park;C.S. Lee;J.T. Kong;M.H.Kim;T.S.Kim;S.H.Lee
20. SISPAD Analysis of Channel-Width Effects in 0.3um Ultra-Thin SOI NMOSFETs C.H. Choi;S.H. Lee;Y.K. Park;J.T. Kong
21. ASIC DESIGN WORKSHOP 신진박사 논문발표대회 및 공개토론회 CubicPlan :Logic 설계자를 위한 계층적 Floorplanning 시스템 장명수;진훈상;이진용;오성환;이상훈
22. 5th ICVC A Simultaneous Switching Noise Analysis System and Its Application to High Speed Memory Module design J.H. Choi;K.H. Kim;J.B. Lee;T.S. Kim;J.T. Kong;S.H. Lee
23. ISCAS New model parameter extraction Environment for the Submicron Circuit models C.H. Choi;J.K. Park;Y.G. Kim;K.H. Kim;S.H. Lee
24. MWSCAS PESE: An Efficient Partition Based Electricla Simulation Environment Y.G. Kim;A. Dharchoudhury;S.M. Kang;K.H. Kim
25. Digital Timing Macromodeling for VLSI Design J.T. Kong;D. Overhauser
26. ISCAS Timing Verificaiton with Nonperiodic Gated Clocking H.B. Kim;E.Y. Chung;J.T. Kong;s.H. Lee
27. ISCAS SENSATION : A New Environment for Automatic Circuit Optimization and Statistical Analysis Y.G. Kim;J.H. Lee;K.H. Kim;S.H. Lee
28. EDAC Development of Multi-Domain/Circuit Optimization System(HISENS) Y.J. Gu;Y.G. Kim;T.S. Kim;S.H. Lee
29. JTC-CSCC Interactive and Knowledge-Assistant Environment for Advanced MOS Model Parameter Extraction C.H. Choi;J.K. Park;Y.G. Kim;K.H. Kim;S.H. Lee