1.0.$\mu$ CMOS SOG로 구현한 직접 디지털 주파수합성기의 성능에 관한 고찰

A study on the Direct Digitral Frequency Synthesizer Implemented in the 1.0$\mu$ CMOS SOG and Its Performance

In this study, two types of the direct digital frequency synthesizers (DDFS) designed and implemented using 1.0.mu.m CMOS gatearray(SOG) technolgoies are interoduced. To analize the effect of the number of phase bits(L), address data bits(A), and DAC bits (D) on the output spectrums of the DDFSs, the NCO-based BCD-DDFS composed of L=24, A=14, and D=8, and the improved binary-DDFS composed of L=24, A=8, and D=10 have been studied. The chips have been designed with and without a noise shapper to reduce spurious noises due to phase truncation and reduced sine ROM in output spectrum.