전자공학회논문지B (Journal of the Korean Institute of Telematics and Electronics B)
- 제31B권5호
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- Pages.73-80
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- 1994
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- 1016-135X(pISSN)
배열 승산기의 속도 형성을 위한 CSA 배열 구조에 관한 연구
A Study on the Design Scheme of CSA Array for the Speed up of Array Multiplier
초록
This paper deals with a new design scheme to reduce the array multiplication time by modifing the structure of the CSA array in the conventional array miltyplier. A circuit with the suggested scheme is designed and simulated. The suggested scheme is to assign the inputs of addend and augend faster than carry input to the CSA. It is shown that the operation time of the CSA array is reduced to 50%.
키워드