Journal of the Korean Institute of Telematics and Electronics B (전자공학회논문지B)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A Study on the Design Scheme of CSA Array for the Speed up of Array Multiplier

배열 승산기의 속도 형성을 위한 CSA 배열 구조에 관한 연구

  • 이용석 (아주대학교 전자공학과) ;
  • 홍근선 (아주대학교 전자공학과) ;
  • 김용덕 (아주대학교 전자공학과)
  • Published : 1994.05.01
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Abstract

This paper deals with a new design scheme to reduce the array multiplication time by modifing the structure of the CSA array in the conventional array miltyplier. A circuit with the suggested scheme is designed and simulated. The suggested scheme is to assign the inputs of addend and augend faster than carry input to the CSA. It is shown that the operation time of the CSA array is reduced to 50%.

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