A Circuit Design of 4:1 Parallel ADC Using Source Coupled FET Logic

Source Coupled FET Logic을 이용한 4:1 병렬 ADC 설계

In this paper, the circuit that has characteristics of high speed and low dissipation is described. A 4:1 parallel ADC is constructed by using the designed SCFL(Source Coupled FET Logic). The results of simulation shows that comparators is obtained integrated nonlinearity, $\pm$28mV, compared with limiting value, $\pm$68mV, at 66NHz input signal and 2Gs/s Niquist rates and this paper describes low power dissipation about 0.43W by reducing the elements in a ADC design.

본 연구에서는 기존의 SCFL(Source Coupled FET Logic)회로보다 고속 저전력 특성을 지닌 회로를 설계하였다. 설계된 SCFL을 이용하여 4:1 병렬 A/D 컨버터를 구성, 시뮬레이션 한 결과 비교기(Comparator 혹은 양자화기)는 66MHz 입력신호와 2GHz 샘플링 주파수에서 Integral Nonlinearity는 $\pm$28mV로 한계치 $\pm$68mV 보다 훨씬 작으며, ADC 설계시 150여개의 소자를 줄여 전력소비 0.43mW를 실현케 하였다.