Journal of the Korean Institute of Telematics and Electronics (대한전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Circuit Extraction from MOS/LSI Mask Layout

집적회로 마스크 도면으로부터의 회로 추출

  • Kim, Sung Soo (Dept. of Elec. Eng., KAIST) ;
  • Kyung, Chong Min (Dept. of Elec. Eng., KAIST)
  • 김성수 (한국과학기술원 전기 및 전자공학과) ;
  • 경종민 (한국과학기술원 전기 및 전자공학과)
  • Published : 1986.06.01
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Abstract

This paper describes the CIREX(CIRcuit EXtractor), an automated CMOS circuit extraction program which provides SPICE2 input file by computing circuit connectivity and transistor dimensions from the CIF file. The CIREX also computes parasitic capacitance and resistance which makes it a valuable tool for timing analysis and detailed circuit simulation. A lattice model is used to calculate the interconnection resistances and substrate capacitances which can be replaced, as an option, by a node model for the worst case timing analysis of the circuit.

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