Proceedings of the Korean Vacuum Society Conference (한국진공학회:학술대회논문집)
- 2014.02a
- /
- Pages.344-344
- /
- 2014
Electrical Characteristic of IGZO Oxide TFTs with 3 Layer Gate Insulator
- Lim, Sang Chul (Electronics and Telecommunications Research Institute (ETRI)) ;
- Koo, Jae Bon (Electronics and Telecommunications Research Institute (ETRI)) ;
- Park, Chan Woo (Electronics and Telecommunications Research Institute (ETRI)) ;
- Jung, Soon-Won (Electronics and Telecommunications Research Institute (ETRI)) ;
- Na, Bock Soon (Electronics and Telecommunications Research Institute (ETRI)) ;
- Lee, Sang Seok (Electronics and Telecommunications Research Institute (ETRI)) ;
- Cho, Kyoung Ik (Electronics and Telecommunications Research Institute (ETRI)) ;
- Chu, Hye Yong (Electronics and Telecommunications Research Institute (ETRI))
- Published : 2014.02.10
Abstract
Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of