Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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The Study for Investigation of the sufficient vertical profile with reducing loading effect for silicon deep trench etching

Vertical Profile Silicon Deep Trench Etch와 Loading effect의 최소화에 대한 연구

  • Kim, Sang-Yong (Dep't of Semiconductor system, Cheong-Ju Campus of Korea Polytechnic College) ;
  • Jeong, Woo-Yang (Dep't of Semiconductor system, Cheong-Ju Campus of Korea Polytechnic College) ;
  • Yi, Keun-Man (Department of Electrical and Electronics Engineering, Cheong-ju University) ;
  • Kim, Chang-Il (Department of Electrical and Electronics Engineering, Chung-ang University)
  • 김상용 (한국 폴리텍 대학 청주캠퍼스 반도체시스템학과) ;
  • 정우양 (한국 폴리텍 대학 청주캠퍼스 반도체시스템학과) ;
  • 이근만 (청주대학교 전기전자공학부) ;
  • 김창일 (중앙대학교 전기전자공학부)
  • Published : 2009.06.18
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Abstract

This paper presents the feature profile evolution silicon deep trench etching, which is very crucial for the commercial wafer process application. The silicon deep trenches were etched with the SF6 gas & Hbr gas based process recipe. The optimized silicon deep trench process resulted in vertical profiles (87o~90o) with loading effect of < 1%. The process recipes were developed for the silicon deep trench etching applications. This scheme provides vertically profiles without notching of top corner was observed. In this study, the production of SF6 gas based silicon deep trench etch process much more strongly than expected on the basis of Hbr gas trench process that have been investigated by scanning electron microscope (SEM). Based on the test results, it is concluded that the silicon deep trench etching shows the sufficient profile for practical MOS FET silicon deep trench technology process.

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