한국전기전자재료학회:학술대회논문집 (Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference)
- 한국전기전자재료학회 2009년도 하계학술대회 논문집
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- Pages.88-89
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- 2009
Trench MOSFET Technology의 Deep Trench 구조에서 WET Cleaning 영향에 대한 연구
The Study of WET Cleaning Effect on Deep Trench Structure for Trench MOSFET Technology
- 김상용 (한국 폴리텍 대학 청주캠퍼스 반도체시스템학과) ;
- 정우양 (한국 폴리텍 대학 청주캠퍼스 반도체시스템학과) ;
- 이근만 (청주대학교 전기전자공학부) ;
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김창일
(중앙대학교 전기전자공학부)
- Kim, Sang-Yong (Dep't of Semiconductor system, Cheong-Ju Campus of Korea Polytechnic College) ;
- Jeong, Woo-Yang (Dep't of Semiconductor system, Cheong-Ju Campus of Korea Polytechnic College) ;
- Yi, Keun-Man (Department of Electrical and Electronics Engineering, Cheong-ju University) ;
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Kim, Chang-Il
(Department of Electrical and Electronics Engineering, Chung-ang University)
- 발행 : 2009.06.18
초록
In this paper, we investigated about wet cleaning effect as deep trench formation methods for Power chip devices. Deep trench structure was classified by two methods, PSU (Poly Stick Up) and Non-PSU structure. In this paper, we could remove residue defect during wet. cleaning after deep trench etch process for non-PSU structure device as to change wet cleaning process condition. V-SEM result showed void image at the trench bottom site due to residue defect and residue component was oxide by EDS analysis. In order to find the reason of happening residue defect, we experimented about various process conditions. So, defect source was that oxide film was re-deposited at trench bottom by changed to hydrophobic property at substrate during hard mask removal process. Therefore, in order to removal residue defect, we added in-situ SCI during hard mask removal process, and defect was removed perfectly. And WLR (Wafer Level Reliability) test result was no difference between normal and optimized process condition.