The formation of nano pillar arrays with p-type silicon using electrochemical etching

Electrochemical etching을 이용한 P형 실리콘에서의 nano pillar arrays 형성

  • Ryu, Han-Hee (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
  • Kong, Seong-Ho (School of Electrical Engineering and Computer Science, Kyungpook National University) ;
  • Kim, Jae-Hyun (Nano Applied Energy Device Laboratory, Daegu-Gyeongbuk Institute of Science and Technology(DGIST))
  • 류한희 (경북대학교 전자전기컴퓨터학부) ;
  • 공성호 (경북대학교 전자전기컴퓨터학부) ;
  • 김재현 (대구경북과학기술원 나노바이오연구부 나노응용에너지소자연구실)
  • Published : 2009.07.14

Abstract

The process conditions for fabricating p-type silicon pillars were optimized by controlling current density, bath temperature. To get best process flexibility for pillar arrays formation, three factors affecting pillar formation were changed. First, the solution bath was designed to keep constant temperature during the experiment irrespective of external temperature. Second, the counter Pt electrode was changed from rod type to mesh to obtain uniform distribution of current density. Third, Cr-Cu alloy electrode instead of Cu was used to increase electrode current density.

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