Analysis of the Interface Trap Effect on Electrical Characteristic and Reliability of SANOS Memory Cell Transistor

SANOS 메모리 셀 트랜지스터에서 Tunnel Oxide-Si Substrate 계면 트랩에 따른 소자의 전기적 특성 및 신뢰성 분석

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.