시스템 내에 존재하는 다중 클럭을 제어하는 테스트 기법에 관한 연구

Test Methodology for Multiple Clocks in Systems

  • 이일장 (성균관대학교 정보통신공학부) ;
  • 김인수 (성균관대학교 정보통신공학부) ;
  • 민형복 (성균관대학교 정보통신공학부)
  • Lee, Il-Jang (Depart. of Information & Communication Engineering, Sungkyunkwan University) ;
  • Kim, In-Soo (Depart. of Information & Communication Engineering, Sungkyunkwan University) ;
  • Min, Hyoung-Bok (Depart. of Information & Communication Engineering, Sungkyunkwan University)
  • 발행 : 2007.07.18

초록

To the Boundary Scan, this architecture in Scan testing of design under the control of boundary scan is used in boundary scan design to support the internal scan chain. The internal scan chain has single scan-in port and single scan-out port that multiple scan chain cannot be used. Internal scan design has multiple scan chains, those chains must be stitched to form a scan chain as this paper. We propose an efficient Boundary Scan test structure for multiple clock testing in design.

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