한국전기전자재료학회:학술대회논문집 (Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference)
- 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
- /
- Pages.93-94
- /
- 2005
Dual Damascene 공정에서 Bottom-up Gap-fill 메커니즘을 이용한 Cu Plating 두께 최적화
Cu Plating Thickness Optimization by Bottom-up Gap-fill Mechanism in Dual Damascene Process
- Yoo, Hae-Young (Chung-Ang Univ.) ;
- Kim, Nam-Hoon (Chosun Univ.) ;
- Kim, Sang-Yong (DongbuAnam Semiconductor Co.) ;
- Chang, Eui-Goo (Chung-Ang Univ.)
- 발행 : 2005.07.07
초록
Cu metallization using electrochemical plating(ECP) has played an important role in back end of line(BEOL) interconnect formation. In this work, we studied the optimized copper thickness using Bottom-up Gap-fill in Cu ECP, which is closely related with the pattern dependencies in Cu ECP and Cu dual damascene process at 0.13
키워드