한국마이크로전자및패키징학회:학술대회논문집 (Proceedings of the International Microelectronics And Packaging Society Conference)
- 한국마이크로전자및패키징학회 2005년도 ISMP
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- Pages.67-88
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- 2005
Mold-Flow Simulation in 3 Die Stack Chip Scale Packaging
- Rhee Min-Woo (Packaging Characterization Center Material & Process development team, R&D Amkor technology Korea)
- 발행 : 2005.09.01
초록
Mold-Flow 3 Die Stack CSP of Mold array packaging with different Gate types. As high density package option such as 3 or 4 die stacking technologies are developed, the major concerning points of mold related qualities such as incomplete mold, exposed wires and wire sweeping issues are increased because of its narrow space between die top and mold surface and higher wiring density. Full 3D rheokinetic simulation of Mold flow for 3 die stacking structure case was done with the rheological parameters acquired from Slit-Die rheometer and DSC of commercial EMC. The center gate showed severe void but corner gate showed relatively better void performance. But in case of wire sweeping related, the center gate type showed less wire sweeping than corner gate types. From the simulation results, corner gate types showed increased velocity, shear stress and mold pressure near the gate and final filling zone. The experimental Case study and the Mold flow simulation showed good agreement on the mold void and wire sweeping related prediction. Full 3D simulation methodologies with proper rheokinetic material characterization by thermal and rheological instruments enable the prediction of micro-scale mold filling behavior in the multi die stacking and other complicated packaging structures for the future application.
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