Ultra low temperature polycrystalline silicon thin film transistor using sequential lateral solidification and atomic layer deposition techniques

  • Lee, J.H. (Basic Research Lab., ETRI) ;
  • Kim, Y.H. (Basic Research Lab., ETRI) ;
  • Sohn, C.Y. (Basic Research Lab., ETRI) ;
  • Lim, J.W. (Basic Research Lab., ETRI) ;
  • Chung, C.H. (Basic Research Lab., ETRI) ;
  • Park, D.J. (Basic Research Lab., ETRI) ;
  • Kim, D.W. (Basic Research Lab., ETRI) ;
  • Song, Y.H. (Basic Research Lab., ETRI) ;
  • Yun, S.J. (Basic Research Lab., ETRI) ;
  • Kang, K.Y. (Basic Research Lab., ETRI)
  • Published : 2004.08.23

Abstract

We present a novel process for the ultra low temperature (<150$^{\circ}C$) polycrystalline silicon (ULTPS) TFT for the flexible display applications on the plastic substrate. The sequential lateral solidification (SLS) was used for the crystallization of the amorphous silicon film deposited by rf magnetron sputtering, resulting in high mobility polycrystalline silicon (poly-Si) film. The gate dielectric was composed of thin $SiO_2$ formed by plasma oxidation and $Al_2O_3$ deposited by plasma enhanced atomic layer deposition. The breakdown field of gate dielectric on poly-Si film showed above 6.3 MV/cm. Laser activation reduced the source/drain resistance below 200 ${\Omega}$/ㅁ for n layer and 400 ${\Omega}$/ㅁ for p layer. The fabricated ULTPS TFT shows excellent performance with mobilities of 114 $cm^2$/Vs (nMOS) and 42 $cm^2$/Vs (pMOS), on/off current ratios of 4.20${\times}10^6$ (nMOS) and 5.7${\times}10^5$ (PMOS).

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