Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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The design of parallel Viterbi decoder for UWB system

UWB system 구현을 위한 병렬 구조 비터비 복호기 설계

  • Lee Kyu Sun (Dept. of Information & Communications, Hanyang University) ;
  • Yoon Sang Hun (Dept. of Information & Communications, Hanyang University) ;
  • Chong Jong-Wha (Dept. of Information & Communications, Hanyang University)
  • 이규선 (한양대학교 정보통신대학원) ;
  • 윤상훈 (한양대학교 정보통신대학원) ;
  • 정정화 (한양대학교 정보통신대학원)
  • Published : 2004.06.01
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Abstract

In this paper, we propose parallel Viterbi decoders applied to UWB(Ultra Wide Band). In consideration of power dissipation and ease of design, we design the architecture, using 132MHz clock instead of 528MHz clock in Baseband. Because Deinterleaver writes and reads the transmitted data per 6Ncbps(The number of coded bits per symbol). using the difference between the number of sampling clock per symbol and the number of coded bits per symbol, we reduce performance degradation of parallel Viterbi decoders. In comparison with using 528MHz clock, the result is little difference.

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