Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)

The Korean Institute of Electrical Engineers (대한전기학회)
권호 표지

2nd-Order 3-Bit Delta-Sigma Modulator For Zero-IF Receivers using DWA algorithm

DWA알고리즘을 적용한 Zero-IF 수신기용 2차 3비트 델타-시그마 변조기

  • 김희준 (경북대학교 전자공학과) ;
  • 이승진 (경북대학교 전자공학과) ;
  • 최치영 (경북대학교 전자공학과) ;
  • 최평 (경북대학교 전자전기컴퓨터공학부)
  • Published : 2003.11.21
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, a second-order 3-bit DSM using DWA(Data Weighted Averaging) algorithm is designed for bluetooth Zero-IF Receiver. The designed circuit has two integrators using a designed OTA, nonoverlapping two-phase clerk generator, 3-bit A/D converter, DWA algorithm and 3-bit D/A converter An ideal model of second-order lowpass DSM with a 3-bit quantizer was configured by using MATLAB, and each coefficients and design specification of each blocks were determined to have 10-bit resolution in 1MHz channel bandwidth. The designed second-order 3-blt lowpass DSM has maximum SNR of 74dB and power consumption is 50mW at 3.3V.

Keywords