대한전자공학회:학술대회논문집 (Proceedings of the IEEK Conference)
- 대한전자공학회 1998년도 하계종합학술대회논문집
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- Pages.875-878
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- 1998
저전력 소모와 테스트 용이성을 고려한 회로 설계
A study on low power and design-for-testability technique of digital IC
초록
In this thesis, we present efficient techniques to reduce the switching activity in a CMOS combinational logic network based on local logic transforms. But this techniques is not appropriate in the view of testability because of deteriorating the random pattern testability of a circuit. This thesis proposes a circuit design method having two operation modes. For the sake of power dissipation(normal operation mode), a gate output switches as rarely as possible, implying highly skewed signal probabilities for 1 or 0. On the other hand, at test mode, signals have probabilities of being 1 or 0 approaching 0.5, so it is possible to exact both stuck-at faults on the wire. Therefore, the goals of synthesis for low power and random pattern testability are achieved. The hardware overhead sof proposed design method are only one primary input for mode selection and AND/OR gate for each redundant connection.
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