Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2001.06b
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- Pages.125-128
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- 2001
Design for Lour pouter Scan-based BIST Using Circuit Partition and Control Test Input Vectors
회로분할과 테스트 입력 벡터 제어를 이용한 저전력 Scan-based BIST 설계
Abstract
In this paper, we propose a low power Scan-based Built-ln Self Test based on circuit partitioning and pattern suppression using modified test control unit. To partition a CUT(Circuit Under Testing), the MHPA(Multilevel Hypergraph Partition Algorithm) is used. As a result of circuit partition, we can reduce the total length of test pattern, so that power consumptions are decreased in test mode. Also, proposed Scan-based BIST architecture suppresses a redundant test pattern by inserting an additional decoder in BIST control unit. A decoder detects test pattern with high fault coverage, and applies it to partitioned circuits. Experimental result on the ISCAS benchmark circuits shows the efficiency of proposed low power BIST architecture.
Keywords