Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.11b
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- Pages.87-90
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- 2000
A Register-Controlled Symmetrical Delay Locked Loop using Hybrid Delay Line
하이브리드 딜레이 라인을 이용한 레지스터 콘트롤 Symmetrical Delay Locked Loop
Abstract
This paper describes a register-controlled symmetrical delay-locked-loop (DLL) using hybrid delay line for use in a high frequency double-data-rate DRAM. The proposed DLL uses a hybrid delay line which can cover two-step delays(coarse/fine delay) by one delay element. The DLL dissipate less power than a conventional dual-loop DLL which use a coarse and a fine delay element and control separately. Additionally, this DLL not only achieves small phase resolution compared to the conventional digital DLL's when it is locked but it also has a great simple delay line compared to a complex dual-loop DLL.
Keywords