Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Modified CMOS Composite Transistors

  • Yu, Young-Gyu (Divisions of Electronic and Information Engineering, Chonbuk National Univ., Chonju) ;
  • Lee, Geun-Ho (Divisions of Electronic and Information Engineering, Chonbuk National Univ., Chonju) ;
  • Kim, Dong-Yong (Divisions of Electronic and Information Engineering, Chonbuk National Univ., Chonju)
  • Published : 2000.11.01
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Abstract

In this paper, we propose two new CMOS composite transistors with an improved operating region by reducing a threshold voltage. The proposed composite transistor 1 and 2 employ a P-type folded composite transistor and an electronic zener diode in order to decrease the threshold voltage, respectively. The simulation has been carried oui using 0.25$\mu\textrm{m}$ n-well process with 2.5V supply voltage.

Keywords