Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)
- 2000.07a
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- Pages.399-402
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- 2000
A Scheduling Approach with Component Selection
- Harashima, Katsumi (Faculty of Engineering, Osaka Institute of Technology) ;
- Satoh, Hisashi (Faculty of Engineering, Osaka Institute of Technology) ;
- Hiro, Daisuke (Faculty of Engineering, Osaka Institute of Technology) ;
- Kutsuwa, Toshiro (Faculty of Engineering, Osaka Institute of Technology)
- Published : 2000.07.01
Abstract
The reduction of chip area and delay is important purpose of Scheduling in High-Level Synthesis. This paper presents a scheduling approach with component selection. After obtaining a initial schedule taking only single-functional u-nits, the component selection of our approach attempts the reduction of chip area and/or delay by the selection more suitable components in a component library using Simulated Annealing.
Keywords