Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1999.07d
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- Pages.1938-1940
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- 1999
Breakdown voltage improvement of LDMOS using Trench Gate structure
Trench Gate 구조를 이용한 LDMOS의 항복전압 개선
- Kim, Hyoung-Woo (School of Electronics Engineering, Ajou University) ;
- Yoo, Seung-Jin (School of Electronics Engineering, Ajou University) ;
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Chung, Sang-Koo
(School of Electronics Engineering, Ajou University)
- Published : 1999.07.19
Abstract
Trench-Gate structures are proposed to improve the breakdown voltage of LDMOS as well as the second breakdown under forward biased gate. Two dimensional device simulator PISCES II has been used to explain the effects of the drift layer thickness on the breakdown voltage of the conventional LDMOS and Trench Gate LDMOS in terms of potential contour lines. The Trench Gate structure has shown improvements in the breakdown voltage by about 44% and 84% for
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