Proceedings of the KIEE Conference (대한전기학회:학술대회논문집)
- 1994.07a
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- Pages.258-261
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- 1994
A Circuit Design for Clamping an Overvoltage in Three-level GTO Inverters
3-레벨 GTO 인버터를 위한 과전압 제한회로 설계
- Suh, Bum-Seok (Dept of Electrical Engineering, Hanyang University) ;
- Hyun, Dong-Seok (Dept of Electrical Engineering, Hanyang University)
- Published : 1994.07.21
Abstract
This paper presents a circuit design far clamping the overvoltages across the GTOs in three-level GTO inverters. The proposed circuit has two roles as follows; one is to minimize the power dissipation in each GTO. It can be achieved by clamping the overvoltage to half that of the DC-link voltage as exactly as possible. The other is to get blocking voltage balancing between the inner GTOs and the outer GTOs.
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