대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
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- Pages.579-581
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- 1988
계층적 논리 회로의 시뮬레이션
Simulation for hierarchical logic network
초록
This paper proposes the logic simulation for hierarchical logic network with function descriptor base data structure and algorithm on which a macro cell is considered as a logic elements. Function descriptor base data structure is useful when many logic elements of which type is same exist in a network, for it lessens the computer memory size used during the simulation. And the proposed simulation algorithm may improve the simulation speed.
키워드