• Journal of the Korean Society of Safety
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• v.37 no.1
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• pp.12-19
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• 2022

Circuit breakers are a crucial factor in ensuring the safety of a Direct Current (DC) grid. One type of DC circuit breaker, the Z-source DC circuit breaker (ZCB), uses a thyristor, which is a type of semiconductor switch. In the event of a fault in the circuit, the ZCB isolates the fault by generating a zero crossing current in the thyristor. The thyristor quickly and actively isolates the fault while generating a zero crossing current, but thyristor switch cannot control turn-off and the allowable current is lower than the current of the mechanical switch. Therefore, it is best to use a mechanical switch with a high allowable current capacity that is capable of on/off control. Due to the slow reaction time of mechanical switches, they may not isolate the fault during the zero crossing current time interval created by the existing circuit. In this case, the zero crossing current time can be increased by using the property that hinders the rapid change in the current of the inductor. This paper will explore whether adding system inductance to increase the zero crossing current time interval is a solution to this problem. The simulation of changing inductor and capacitor (LC) of the circuit is repeated to find an optimal change in the zero crossing current time according to the LC change and provides an inductor and capacitor range optimized for a specific load. The inductor and capacitor range are expected to provide optimization information in the form LC values for future applications of ZCB's using a mechanical switch.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.143-148
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• 2020

In the case of a system that detects and controls the phase of an alternating voltage, the analog control method compensates the phase offset part by filtering for the detected phase and applies it to the control. However, in the digital control method, precise control cannot be achieved due to an error between the operating frequency of the microprocessor or the microcontroller and the input phase time when controlled using such phase detection. In general, when the method used is a certain time, the accumulated error is compensated and adjusted at random. To solve this problem, a method of detecting a zero point in real time and compensating for the operating frequency of the microprocessor is needed. Therefore, the research to be performed in this paper to reduce these errors and apply them to precise digital control is as follows. 1) Research on how to implement Zero Crossing Detection algorithm through simulation modeling to compensate the zero point to match the operating frequency through detection. 2) A study on the method of detecting zero points in real time through the Zero Crossing Detection design using a microcontroller and compensating for the operating frequency of the microprocessor. 3) A study on the estimation of the rotor position of BLDC motors using the Zero Crossing Detection circuit.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1094-1096
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• 1987

Zero-crossing analysis techniques have been applied to speech recognition. Zero-crossing rate, level-crossing rate and differentiated zero-crossing rate in time domain we used in analyzing speech signals. Speech samples could be stored in memory buffer in real time.

• Journal of Power Electronics
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• v.19 no.1
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• pp.278-287
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• 2019

In this study, a zero-crossing spike current issue in a totem-pole bridgeless power factor correction (PFC) converter is comprehensively investigated for the first time. Spike current occurs when input voltage crosses zero, becomes a noise source, and causes severe common mode emission issues. A generation mechanism for electromagnetic interference (EMI) is presented to investigate the EMI problem caused by zero-crossing issue, and a noise spectrum due to this issue is predicted by a theoretical analysis based on the Fourier coefficient of an approximate spike current waveform. Furthermore, a noise reduction method is proposed and then improved to reduce the spike current. Experimental measurements are implemented on a GaN-based totem-pole bridgeless PFC converter, and the spike current can be effectively suppressed through the proposed method. Furthermore, the noise spectrums measured without and with the reduced zero-crossing spike current are compared. Experimental results validate the analysis of the noise spectrum caused by the zero-crossing spike current issue.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.634-636
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• 2008

This paper proposes a frequency detection method based on an advanced zero-crossing technique. Zero-crossing method for detecting frequency is one of the most widely used methods today. Although it is simple to apply, it requires extra hardware in implementation due to its limitations in accuracy. The proposed method models the error generated during zero crossing linearization and compensated for it in real time which makes it simple and accurate. The validity of the method and its applicability in anti-islanding detection of distributed generators was confirmed through simulation.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.389-390
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• 2007

In this paper, we propose a modified watershed algorithm to obtain exact edge of region. The proposed method adjusts priority at zero-crossing point of gradient in order to make the point of region decision time postponed. We compare the proposed method with a previous method and prove that this method can extract more correct edge of region.

• Journal of Power Electronics
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• v.16 no.5
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• pp.1661-1668
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• 2016

A fixed off-time controlled high power factor ac-dc LED driver is proposed in this paper, which employs a novel zero-crossing-compensation (ZCC) circuit based on a fixed off-time controlled scheme. Due to the parasitic parameters of the system, the practical waveforms have a dead region. By detecting the zero-crossing boundary, the proposed ZCC circuit compensates the control signal VCOMP within the dead region, and is invalid above this region. With further optimization of the parameters KR and Kτ of the ZCC circuit, the dead zone can be eliminated and lower THD is achieved. Finally, the chip is implemented in HHNEC 0.5μm 5V/40V HVCMOS process, and a prototype circuit, delivering 7~12W of power to several 3-W LED loads, is tested under AC input voltage ranging from 85V to 265V. The test results indicate that the average total harmonic distortion (THD) of the entire system is approximately 10%, with a minimum of 5.5%, and that the power factor is above 0.955, with a maximum of 0.999.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.12
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• pp.1248-1255
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• 2003

High-speed QPSK demodulator has been one important design objective of any wireless communication systems, especially those offering broadband multimedia service. This paper describes Zero-Crossing IF-level(ZCIF) QPSK demodulator for high-speed wireless communications, and its hardware structures are discussed. ZCIF QPSK demodulator is mainly composed of symbol time circuit and carrier recovery circuit to estimate timing and phase-offsets. There are various schemes. Among them, we use Gardner algorithm and Decision-Directed carrier recovery algorithm which is most efficient scheme to warrant the fast acquisition and tracking to fabricate FPGA chip. The testing results of the implemented onto CPLD-FLEX10K chip show demodulation speed is reached up to 2.6［Mbps］. Actually in case of designing by ASIC, its speed may be faster than CPLD by 5 times. Therefore, it is possible to fabricate the ZCIF QPSK demodulator with speed of 10 Mbps.

• MALSORI
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• no.59
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• pp.69-87
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• 2006

Among the conventional time-scale modification (TSM) methods, the synchronized overlap and add (SOLA) method is widely used due to its good performance relative to computational complexity But the SOLA method remains complex due to its synchronization procedure using the normalized cross-correlation function. In this paper, we introduce a computationally efficient SOLA method utilizing 3 level center clipping method, as well as zero-crossing and level-crossing information. The result of subjective preference test indicates that the proposed method can reduce the computational complexity by over 80% compared with the conventional SOLA method without serious degradation of synthesized speech quality.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.134-141
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• 2022

This study presents a method for reducing current distortion that occurs when a dual-buck inverter generates reactive power. Dual-buck inverters, which are only capable of unity power factor operation, can generate reactive power capabilities by modifying a modulation technique. However, under non-unity power factor conditions, current distortion occurs at zero-crossing points of grid voltage and output current. This distortion is caused by parasitic capacitors, dead-time, and discontinuous conduction mode operation. This study proposes a modified modulation method to alleviate the current distortion at zero-crossing point of the grid voltage. A repetitive controller is applied to reduce this distortion of the output current. A 1 kVA prototype is built and tested. Simulation and experimental results demonstrate the effectiveness of the proposed method.