• Title/Summary/Keyword: zero modulation

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Analysis of Common Mode Voltages at Diode Rectifier/Z-Source Inverter System (다이오드 정류기/Z-소스 인버터 시스템의 공통모드 전압 해석)

  • Tran, Quang-Vinh;Chun, Tae-Won;Lee, Hong-Hee
    • The Transactions of the Korean Institute of Power Electronics
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    • v.14 no.4
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    • pp.285-292
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    • 2009
  • In this paper, when ac motors are driven by the diode rectifier/Z-source inverter system, the common-mode voltages of system are analyzed in details under both the shoot-through state and non-shoot-through state through equivalent circuits. Then a modified space vector modulation strategy is suggested for attenuating the negative common-mode voltage by eliminating the zero voltage vector, and also controlling the shoot-through time. Through the simulation studies with PSIM and experiments with 32-bit DSP, it is verified that the negative common-mode voltage can be reduced by more than 50%.

Model Predictive Power Control of a PWM Rectifier for Electromagnetic Transmitters

  • Zhang, Jialin;Zhang, Yiming;Guo, Bing;Gao, Junxia
    • Journal of Power Electronics
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    • v.18 no.3
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    • pp.789-801
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    • 2018
  • Model predictive direct power control (MPDPC) is a widely recognized high-performance control strategy for a three-phase grid-connected pulse width modulation (PWM) rectifier. Unlike those of conventional grid-connected PWM rectifiers, the active and reactive powers of permanent magnet synchronous generator (PMSG)-connected PWM rectifiers, which are used in electromagnetic transmitters, cannot be calculated as the product of voltage and current because the back electromotive force (EMF) of the generator cannot be measured directly. In this study, the predictive power model of the rectifier is obtained by analyzing the relationship among flux, back EMF, active/reactive power, converter voltage, and stator current of the generator. The concept of duty cycle control in the proposed MPDPC is introduced by allocating a fraction of the control period for a nonzero vector and rest time for a zero vector. When nonzero vectors and their duration in the predefined cost function are simultaneously evaluated, the global power ripple minimization is obtained. Simulation and experimental results prove that the proposed MPDPC strategy with duty cycle control for the PMSG-connected PWM rectifier can achieve better control performance than the conventional MPDPC-SVM with grid-connected PWM rectifier.

Analysis of high-frequency resonant Inverter character using efficient ozonizer (고효율 오존생기용 고주파 공진형 인버터의 특성 해석)

  • Kim, Young-Hoon;Hwang, Young-Min;Noh, In-Bae;Kim, Young-Bin;Heo, Tae-Won;Woo, Jung-In
    • Proceedings of the KIEE Conference
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    • 2002.11d
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    • pp.246-248
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    • 2002
  • This paper presents a high-frequency voltage source inverter for silent corona discharge ozonizer application, which is characterized by the power control based on pulse density modulation (PDM). The PDM inverter produces either a square -wave ac-voltage state or a zero-voltage state at its ac terminals to control the average output voltage under constant do voltage and operating frequency. This results in a wide range of power control in the silent corona discharge load with a strong nonlinear characteristics. And proposed addition circuit for maintain discharge on the center of the airgap. In this paper, schemed equivalent electric circuit of the discharge electrode for simulation. Finally, the effectiveness of this discharge tube character of silent corona ozonizer is investigated in the simulation results.

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Efficiency Improvement of the Fixed-Complexity Sphere Decoder

  • Mohaisen, Manar;Chang, Kyung-Hi
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.5 no.3
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    • pp.494-507
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    • 2011
  • In this paper, we propose two schemes to reduce the complexity of fixed-complexity sphere decoder (FSD) algorithm in the ordering and tree-search stages, respectively, while achieving quasi-ML performance. In the ordering stage, we propose a QR-decomposition-based FSD signal ordering based on the zero-forcing criterion (FSD-ZF-SQRD) that requires only a few number of additional complex flops compared to the unsorted QRD. Also, the proposed ordering algorithm is extended using the minimum mean square error (MMSE) criterion to achieve better performance. In the tree-search stage, we introduce a threshold-based complexity reduction approach for the FSD depending on the reliability of the signal with the largest noise amplification. Numerical results show that in 8 ${\times}$ 8 MIMO system, the proposed FSD-ZF-SQRD and FSD-MMSE-SQRD only require 19.5% and 26.3% of the computational efforts required by Hassibi's scheme, respectively. Moreover, a third threshold vector is outlined which can be used for high order modulation schemes. In 4 ${\times}$ 4 MIMO system using 16-QAM and 64-QAM, simulation results show that when the proposed threshold-based approach is employed, FSD requires only 62.86% and 53.67% of its full complexity, respectively.

The Control of Z-Source Inverter for using DC Renewable Energy (직류 대체에너지 활용을 위한 Z-원 인버터 제어)

  • Park, Young-San;Bae, Cherl-O;Nam, Taek-Kun
    • Journal of the Korean Society of Marine Environment & Safety
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    • v.13 no.2 s.29
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    • pp.169-172
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    • 2007
  • This paper presents circuit models and control algorithms of distributed generation system(DGS) which consists of Z-type converter and PWM inverter. Z-type converter which employs both the L and C passive components and shoot-through zero vectors instead qf the conventional DC/DC converter in order to step up DC-link voltage. Discrete time sliding mode control with the asymptotic observer is used for current control. This system am be used for power conversion of DC renewable energy.

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Analysis, Design and Implementation of a Soft Switching DC/DC Converter

  • Lin, Bor-Ren
    • Journal of Power Electronics
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    • v.13 no.1
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    • pp.20-30
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    • 2013
  • This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

Analysis and Implementation of a New ZVS DC Converter for Medium Power Application

  • Lin, Bor-Ren;Shiau, Tung-Yuan
    • Journal of Electrical Engineering and Technology
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    • v.9 no.4
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    • pp.1296-1308
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    • 2014
  • This paper presents a new zero voltage switching (ZVS) converter for medium power and high input voltage applications. Three three-level pulse-width modulation (PWM) circuits with the same power switches are adopted to clamp the voltage stress of MOSFETs at $V_{in}/2$ and to achieve load current sharing. Thus, the current stresses and power ratings of transformers and power semiconductors at the secondary side are reduced. The resonant inductance and resonant capacitance are resonant at the transition interval such that active switches are turned on at ZVS within a wide range of input voltage and load condition. The series-connected transformers are adopted in each three-level circuit. Each transformer can work as an inductor to smooth the output current or a transformer to achieve the electric isolation and power transfer. Thus, no output inductor is needed at the secondary side. Three center-tapped rectifiers connected in parallel are used at the secondary side to achieve load current sharing. Compared with the conventional parallel three-level converters, the proposed converter has less switch counts. Finally, experiments based on a 1.44kW prototype are provided to verify the operation principle of proposed converter.

A Study on Performance Enhancement of Selection Combined Hybrid Sequential Deconvolution and SC-FDE for Single Carrier System (선택적 결합 기법을 활용하여 순차적 역컨벌루션과 단일반송파 수신기를 하이브리드하게 사용한 단일반송파 시스템 성능 향상에 관한 연구)

  • Jung, Hyeok-Koo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.37 no.5A
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    • pp.305-310
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    • 2012
  • This paper proposes a selection combined hybrid sequential deconvolution and single carrier modulation with a zero forcing frequency domain equalizer for single carrier transmission system in order to enhance performance. Selection combining method is an algorithm of antenna space diversities, the receiver can choose the best channel environment only with the increase of the number of antennas, but a baseband structure is the same as the traditional receiver architecture. Simulation results show that the proposed algorithm has a better performance rather than the traditional single carrier transmission with a frequency domain equalizer.

Analysis and Implementation of a New Three-Level Converter

  • Lin, Bor-Ren;Nian, Yu-Bin
    • Journal of Power Electronics
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    • v.14 no.3
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    • pp.478-487
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    • 2014
  • This study presents a new interleaved three-level zero-voltage switching (ZVS) converter for high-voltage and high-current applications. Two circuit cells are operated with interleaved pulse-width modulation in the proposed converter to reduce the current ripple at the input and output sides, as well as to decrease the current rating of output inductors for high-load-current applications. Each circuit cell includes one half-bridge converter and one three-level converter at the primary side. At the secondary side, the transformer windings of two converters are connected in series to reduce the size of the output inductor or switching current in the output capacitor. Based on the three-level circuit topology, the voltage stress of power switches is clamped at $V_{in}/2$. Thus, MOSFETs with 500 V voltage rating can be used at 800 V input voltage converters. The output capacitance of the power switch and the leakage inductance (or external inductance) are resonant at the transition interval. Therefore, power switches can be turned on under ZVS. Finally, experiments verify the effectiveness of the proposed converter.

Efficiency Improvement of the Fixed-complexity Sphere Decoder

  • Mohaisen, Manar;Chang, Kyung-Hi
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.5 no.2
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    • pp.330-343
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    • 2011
  • In this paper, we propose two schemes to reduce the complexity of fixed-complexity sphere decoder (FSD) algorithm in the ordering and tree-search stages, respectively, while achieving quasi-ML performance. In the ordering stage, we propose a QR-decomposition-based FSD signal ordering based on the zero-forcing criterion (FSD-ZF-SQRD) that requires only a few number of additional complex flops compared to the unsorted QRD. Also, the proposed ordering algorithm is extended using the minimum mean square error (MMSE) criterion to achieve better performance. In the tree-search stage, we introduce a threshold-based complexity reduction approach for the FSD depending on the reliability of the signal with the largest noise amplification. Numerical results show that in $8{\times}8$ MIMO system, the proposed FSD-ZF-SQRD and FSD-MMSE-SQRD only require 19.5% and 26.3% of the computational efforts required by Hassibi’s scheme, respectively. Moreover, a third threshold vector is outlined which can be used for high order modulation schemes. In $4{\times}4$ MIMO system using 16-QAM and 64-QAM, simulation results show that when the proposed threshold-based approach is employed, FSD requires only 62.86% and 53.67% of its full complexity, respectively.