• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.830-833
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• 2003

This paper describes the fabrication and characteristics of 3C-SiCOI sotctures by SDB and etch-back technology for high-temperature MEMS applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si(001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The wafer bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR. The strength of the bond was measured by tensile strengthmeter. The bonded interface was also analyzed by SEM. The properties of fabricated 3C-SiCOI structures using etch-back technology in TMAH solution were analyzed by XRD and SEM. These results indicate that the 3C-SiCOI structure will offers significant advantages in the high-temperature MEMS applications.

• Laser Solutions
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• v.12 no.3
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• pp.1-6
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• 2009

This paper describes the method for the fabrication of micro dot array on a plastic mold steel using DPSS (diode pumped solid-states) UV laser and wet etching process. We suggest the process of the ablation of a photoresist (PR) coated on plastic mold steel and wet etching process using solutions of various concentrations of $FeCl_3$, $HNO_3$ in water as etchant. This method makes it possible to fabricate metallic roller mold because the microstructures are directly fabricated on the metal surface. In the range of operating conditions studied, $17\;{\mu}J$ laser pulse energy and 50 ms laser exposure time, an etchant containing 40wt% $FeCl_3$, 5wt% $HNO_3$ and etch time for 45 s gave the $10\;{\mu}m$ of micro dot pattern on plastic mold steel.

• Proceedings of the KOSOMBE Conference
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• v.1998 no.11
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• pp.147-148
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• 1998

In this paper, we developed the process for depth-probe type silicon microelectrode arrays. The process consists of four mask steps only. The steps are for defining sites, windows, and for shaping probe using plasma etch from above, and for shaping using wet etch from below, respectively. The probe thickness is controlled by dry etching, not by impurity diffusion. We used gold electrodes with a triple dielectric system consisting of oxide/nitride/oxide. The shank of the probe taper from 200um to tens of urn tip and has 30 um thickness.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.65-65
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• 1999

Dry etching technique provides more easy controllability on the etch profile such as anisotropic etching than wet etching process and the results of lots of researches on the characterization of various plasmas or ion beams for semiconductor etching have been reported. Chlorine-based plasmas or chlorine ion beam have been often used to etch several semiconductor materials, in particular Si-based materials. We have studied the effect of He flow rate on the Si and SiO2 dry etching using chlorine-based plasma. Experiments were performed using reactive ion etching system. RF power was 300W. Cl2 gas flow rate was fixed at 58.6 sccm, and the He flow rate was varied from 0 to 120 sccm. Fig. 1 presents the etch depth of si layer versus the etching time at various He flow rate. In case of low He flow rate, the etch rate was measured to be negligible for both Si and SiO2. As the He flow increases over 30% of the total inlet gas flow, the plasma state becomes stable and the etch rate starts to increase. In high Ge flow rate (over 60%), the relation between the etch depth and the time was observed to be nearly linear. Fig. 2 presents the variation of the etch rate depending on the He flow rate. The etch rate increases linearly with He flow rate. The results of this preliminary study show that Cl2/He mixture plasma is good candidate for the controllable si dry etching.

• Proceedings of the KIEE Conference
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• 2001.07c
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• pp.1924-1926
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• 2001

A novel wet release process ($\mu$ CARP - Micro Channel Assisted Release Process) for releasing an extreme large-area plate structure without etching hole is proposed and experimented. Etching holes in conventional process reduce a effective area and degrade an optical characteristics by a diffraction. In addition, as the area of a released structure increases, the stietion becomes more serious. The proposed process resolves these problems by the introduction of a micro fluidic channel beneath the structure which will be released. In this paper, a 5 mm${\times}$5mm-single crystal silicon plate structure was released by the proposed $\mu$CARP without etch holes on the structure. The variation in etching time with respect to the of the introduced micro channel is also examined. This process is expected to be beneficial for the actuator of a nano-scale data storage and the scanning mirror.

• Journal of the Semiconductor & Display Technology
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• v.15 no.1
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• pp.17-21
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• 2016

EUV (Extreme Ultraviolet) pellicle which protects a mask from contamination became a critical issue for the application of EUV lithography to high-volume manufacturing. However, researches of EUV pellicle are still delayed due to no typical manufacturing methods for large-scale EUV pellicle. In this study, EUV pellicle membrane manufacturing method using not only KOH (potassium hydroxide) wet etching process but also a water bath was suggested for uniform etchant temperature distribution. KOH wet etching rates according to KOH solution concentration and solution temperature were confirmed and proper etch condition was selected. After KOH wet etching condition was set, $5cm{\times}5cm$ SiNx (silicon nitride) pellicle membrane with 80% EUV transmittance was successfully manufactured. Transmittance results showed the feasibility of wet etching method with water bath as a large-scale EUV pellicle manufacturing method.

• Korean Journal of Materials Research
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• v.20 no.8
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• pp.423-428
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• 2010

This study shows the effects of deionized (DI) rinse and oxide HF wet etch processes on silicon substrate during a photolithography process. We found a fail at the wafer center after DI rinse step, called Si pits, during the fabrication of a complementary metal-oxide-semiconductor (CMOS) device. We tried to find out the mechanism of the Si pits by using the silicon wafer on CMOS fabrication and analyzing the effects of the friction charge induced by the DI rinsing. The key parameters of this experiment were revolution per minute (rpm) and time. An incubation time of above 10 sec was observed for the formation of Si pits and the rinsing time was more effective than rpm on the formation of the Si pits. The formation mechanism of the Si pits and optimized rinsing process parameters were investigated by measuring the charging level using a plasma density monitor. The DI rinse could affect the oxide substrate by a friction charging phenomenon on the photolithography process. Si pits were found to be formed on the micro structural defective site on the Si substrate under acceleration by developed and accumulated charges during DI rinsing. The optimum process conditions of DI rinse time and rpm could be established through a systematic study of various rinsing conditions.

• Korean Journal of Optics and Photonics
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• v.8 no.4
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• pp.345-352
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• 1997

Recently, in designing optical mask such as 4GDRAM, the scattering effect of electromagnetic wave must be considered. For this reason we claculated directly the mask function using the finite difference time domain(FDTD) method. The modification of image theory with this new mask function could explain clearly the scattering effect at the etched side wall of the submicron optical mask. The characteristics of the various type of alternating PSM were investigated. According to the simulation, the dual wet etch process was the most useful fabrication technique to overcoe the light scattering off at the shifted opening.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2005.10a
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• pp.182-185
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• 2005

Indentation pattern and line pattern were machined on borosilicate(Pyrex 7740 glass) surface using the combination of mechanical machining by $Nanoi-indenter\circledR$ XP and HF wet etching, and a etch-mask effect of the affected layer of the nano-scratched and indented Pyrex 7740 glass surface was investigated. In this study, effects of indentation and scratch process with etching time on the morphologies of the indented and scratched surfaces after isotropic etching were investigated from an angle of deformation energies.

• ETRI Journal
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• v.27 no.3
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• pp.304-311
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• 2005

We report on the fabrication of an AlGaAs/InGaAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) using a dielectric-defined process. This process was utilized to fabricate $0.12\;{\mu}m\;{\times}\;100 {\mu}m$ T-gate PHEMTs. A two-step etch process was performed to define the gate footprint in the $SiN_x$. The $SiN_x$ was etched either by dry etching alone or using a combination of wet and dry etching. The gate recessing was done in three steps: a wet etching for removal of the damaged surface layer, a dry etching for the narrow recess, and wet etching. A structure for the top of the T-gate consisting of a wide head part and a narrow lower layer part has been employed, taking advantage of the large cross-sectional area of the gate and its mechanically stable structure. From s-parameter data of up to 50 GHz, an extrapolated cut-off frequency of as high as 104 GHz was obtained. When comparing sample C (combination of wet and dry etching for the $SiN_x$) with sample A (dry etching for the $SiN_x$), we observed an 62.5% increase of the cut-off frequency. This is believed to be due to considerable decreases of the gate-source and gate-drain capacitances. This improvement in RF performance can be understood in terms of the decrease in parasitic capacitances, which is due to the use of the dielectric and the gate recess etching method.