• 한국전기전자재료학회논문지
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• 제25권12호
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• pp.1015-1020
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• 2012

Resistance of the front electrode is the highest proportion of the ingredients of the series resistance in crystalline silicon solar cell. While resistance of the front electrode is decreased with larger area, it induces the optical loss, causing the conversion efficiency drop. Therefore the front electrode with high aspect ratio increasing its height and decreasing is necessary for high-efficiency solar cell in considering shadowing loss and resistance of front electrode. In this paper, we used the screen printing method to form high aspect ratio electrode by multiple printing. Screen printing is the straightforward technology to establish the electrodes in silicon solar cell fabrication. The several printed front electrodes with Ag paste on silicon wafer showed the significantly increased height and slightly widen finger. As a result, the resistance of the front electrode was decreased with multiple printing even if it slightly increased the shadowing loss. We showed the improved electrical characteristics for c-Si solar cell with repeatedly printed front electrode by 0.5%. It lays a foundation for high efficiency solar cell with high aspect ratio electrode using screen printing.

• 한국전기전자재료학회논문지
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• 제26권4호
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• pp.271-274
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• 2013

Power Metal Oxide Semiconductor Field Effect Transistor's (MOSFETs) are well known for superior switching speed, and they require very little gate drive power because of the insulated gate. In these respects, power MOSFETs approach the characteristics of an "ideal switch". The main drawback is on-resistance RDS(on) and its strong positive temperature coefficient. While this process has been driven by market place competition with operating parameters determined by products, manufacturing technology innovations that have not necessarily followed such a consistent path have enabled it. This treatise briefly examines metal oxide semiconductor (MOS) device characteristics and elucidates important future issues which semiconductor technologists face as they attempt to continue the rate of progress to the identified terminus of the technology shrink path in about 2020. We could find at the electrical property as variation p base dose. Ultimately, its ON state voltage drop was enhanced also shrink chip size. To obtain an optimized parameter and design, we have simulated over 500 V Field ring using 8 Field rings. Field ring width was $3{\mu}m$ and P base dose was $1e15cm^2$. Also the numerical multiple $2.52cm^2$ was obtained which indicates the doping limit of the original device. We have simulated diffusion condition was split from $1,150^{\circ}C$ to $1,200^{\circ}C$. And then $1,150^{\circ}C$ diffusion time was best condition for break down voltage.

• Journal of Microbiology and Biotechnology
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• 제25권3호
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• pp.381-385
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• 2015

In the present study, drop-on-demand two-dimensional patterning of unstained and stained bacterial cells on untreated clean wafers was newly conducted using an electrospray pulsed jet. We produced various spotted patterns of the cells on a silicon wafer by varying the experimental conditions, such as the frequency, flow rate, and translational speed of the electrospray system in a two-dimensional manner. Specifically, the electrospray's pulsed jet of cell solutions produced alphabetical patterns consisting of spots with a diameter of approximately $10{\mu}m$, each of which contained a single or a small number of viable bacteria. We tested the viability of the patterned cells using two visualization methods. This pattering technique is newly tested here and it has the potential to be applied in a variety of cell biology experiments.

• Transactions on Electrical and Electronic Materials
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• 제3권2호
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• pp.10-15
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• 2002

In this paper, the electrical characteristics of fabricated p+-n junction diode are demonstrated and interpreted with different theoretical calculations. Dopants distribution by boron ion implantation on silicon wafer were simulated with TRIM-code and ICECaEM simulator. In order to make electrical activation of implanted carriers, thermal annealing treatments are carried out by RTP method for 1min. at $1000^{circ}C$ under inert $N_2$ gas condition. In this case, profiles of dopants distribution before and after heat treatments in the substrate are observed from computer simulations. In the I-V characteristics of fabricated diodes, an analytical description method of a new triangular junction model is demonstrated and the results with calculated triangular junction are compared with measured data and theoretical calculated results of abrupt junction. Forward voltage drop with new triangular junction model is lower than the case of abrupt junction model. In the C-V characteristics of diode, the calculated data are compared with the measured data. Another I-V characteristics of diodes are measured after proton implantation in electrical isolation method instead of conventional etching method. From the measured data, the turn-on characteristics after proton implantation is more improved than before proton implantation. Also the C-V characteristics of diode are compared with the measured data before proton implantation. From the results of measured data, reasonable deviations are showed. But the C-V characteristics of diode after proton implantation are deviated greatly from the calculated data because of leakage currents in defect regions and layer shift of depletion by proton implantation.

• 한국광학회지
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• 제18권1호
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• pp.74-78
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• 2007

본 논문에서는 포토마스크 후면에 위상 패턴을 형성하여 웨이퍼 상 CD(critical dimension) 균일도를 개선할 수 있는 투과율 조절 포토마스크 기술을 ArF 리소그래피에 적용한 결과에 대하여 보고한다. 위상 패턴 조밀도에 따른 노광 광세기 변화 계산에 포토마스크 후면으로부터 포토마스크 전면까지의 광의 전파를 고려하여 ArF 파장에서의 위상 패턴 조밀도에 따른 노광 광세기 저하에 관한 실험결과를 이론적으로 재현할 수 있었다. 본 기술을 ArF 리소그래피에 적용하여 DRAM(Dynamic Random Access Memory)의 한 주요 레이어에 대해 필드 내 CD 균일도를 $3{\sigma}$ 값으로 13.8 nm에서 9.7 nm로 개선하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.171-175
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• 2001

Chemical mechanical polishing(CMP) process has been widely used to planarize dielectrics and metal, which can apply to employed in integrated circuits for sub-micron technology. Despite the increased use of CMP process, it is difficult to accomplish the global planarization of free-defects in inter level dielectrics and metal. Especially, defects like (micro-scratch) lead to severe circuit failure, and affects yield. Current conditioning method - bladder type, orbital pad motion - usually provides unsuitable pad profile during ex-situ conditioning near the end of pad life. Since much of the pad wear occurs by the mechanism of bladder tripe conditioning and its orbital motion without rotation, we need to implement new ex-situ conditioner which can prevent abnormal regional force on pad caused by bladder-type and also need to rotate the pad during conditioning. Another important study of ADPC is related to the orbital scratch of which source is assumed as diamond grit dropped from the strip during ex-situ conditioning. Scratch from diamond grit damaged wafer severely so usual1y scraped. Figure 1 shows the typical shape of scratch damaged from diamond. We suspected that intensive forces to the edge area of bladder type stripper accelerated the drop of Diamond grit during conditioning, so new designed Flat stripper was introduced.

• 한국정보통신학회논문지
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• 제12권7호
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• pp.1227-1234
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• 2008

본 논문에서는 자동차 전장용 Power IC, 디스플레이 구동 칩, CMOS 이미지 센서 등의 응용분야에서 필요로 하는 동기식 256-bit OTP(one-time programmable) 메모리를 설계하였다. 동기식 256-bit OTP 메모리의 셀은 고전압 차단 트랜지스터 없이 안티퓨즈인 NMOS 커패시터와 액세스 트랜지스터로 구성되어 있다. 기존의 3종류의 전원 전압을 사용하는 대신 로직 전원 전압인 VDD(=1.5V)와 외부 프로그램 전압인 VPPE(=5.5V)를 사용하므로 부가적인 차단 트랜지스터의 게이트 바이어스 전압 회로를 제거하였다. 그리고 프로그램시 전류 제한 없이 전압 구동을 하는 경우 안티퓨즈의 ON 저항 값과 공정 변동에 따라 프로그램 할 셀의 부하 전류가 증가한다. 그러므로 프로그램 전압은 VPP 전원 선에서의 저항성 전압 감소로 인해 상대적으로 증가하는 문제가 있다. 그래서 본 논문에서는 전압 구동 대신 전류 구동방식을 사용하여 OTP 셀을 프로그램 할 때 일정한 부하전류가 흐르게 한다. 그래서 웨이퍼 측정 결과 VPPE 전압은 5.9V에서 5.5V로 0.4V 정도 낮출 수 있도록 하였다. 또한 기존의 전류 감지 증폭기 대신 Clocked 인버터를 사용한 감지 증폭기를 사용하여 회로를 단순화시켰다. 동기식 256-bit OTP IP는 매그나칩 반도체 $0.13{\mu}m$ 공정을 이용하여 설계하였으며, 레이아웃 면적은 $298.4{\times}3.14{\mu}m2$이다.

• 한국전산구조공학회논문집
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• 제32권2호
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• pp.103-108
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• 2019

본 논문에서는 비평형 분자동역학 시뮬레이션 기법을 사용하여 알루미늄 박막과 실리콘 웨이퍼 간 열경계저항을 예측하였다. 실리콘의 끝 단 고온부에 열을 공급하고, 같은 양의 열을 알루미늄 끝 단 저온부에서 제거하여 경계면을 통한 열전달이 일어나도록 하였으며, 실리콘 내부와 알루미늄 내부의 선형 온도 변화를 계산함으로써 경계면에서의 온도 차이에 따른 열저항 값을 구하였다. 300K 온도에서 $5.13{\pm}0.17m^2{\cdot}K/GW$의 결과를 얻었으며, 이는 열유속 조건의 변화와 무관함을 확인하였다. 아울러, 펨토초 레이저 기반의 시간영역 열반사율 기법을 사용하여 열경계저항 값을 실험적으로 구하였으며, 시뮬레이션 결과와 비교 검증하였다. 전자빔 증착기를 사용하여 90nm 두께의 알루미늄 박막을 실리콘(100) 웨이퍼 표면에 증착하였으며, 유한차분법을 이용한 수치해석을 통해 열전도 방정식의 해를 구해 실험결과와 곡선맞춤 함으로써 열경계저항을 정량적으로 평가하고 나노스케일에서의 열전달 현상에 관한 특징을 살펴보았다.