• Korean Journal of Materials Research
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• v.11 no.3
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• pp.159-163
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• 2001

The success of SDB (silicon wafer direct bonding) technology can be estabilished by bonding on the bonded interface with no defects and Preventing temperature dependent bubbles. In this research, we observed the behavior of the intrinsic bubbles by transmitting the infrared light and the increase of the bubble pressure was found. And, the $SiO_2$-$SiO_2$ bonded wafer was achieved, which generates no intrinsic bubbles in the annealing under the atmospheric pressure. The intrinsic bubbles in the $SiO_2$-$SiO_2$ bonded wafer were generated in the annealing in the ultra high vacuum. This experimental result shows the relation between the bubble growth and the pressure.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.8
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• pp.700-704
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• 2003

This paper describes on characteristics of 2" 3C-SiC wafer bonding using PECVD (plasma enhanced chemical vapor deposition) oxide and HF (hydrofluoride acid) for SiCOI (SiC-on-Insulator) structures and MEMS (micro-electro-mechanical system) applications. In this work, insulator layers were formed on a heteroepitaxial 3C-SiC film grown on a Si (001) wafer by thermal wet oxidation and PECVD process, successively. The pre-bonding of two polished PECVD oxide layers made the surface activation in HF and bonded under applied pressure. The bonding characteristics were evaluated by the effect of HF concentration used in the surface treatment on the roughness of the oxide and pre-bonding strength. Hydrophilic character of the oxidized 3C-SiC film surface was investigated by ATR-FTIR (attenuated total reflection Fourier transformed infrared spectroscopy). The root-mean-square suface roughness of the oxidized SiC layers was measured by AFM (atomic force microscope). The strength of the bond was measured by tensile strength meter. The bonded interface was also analyzed by IR camera and SEM (scanning electron microscope), and there are no bubbles or cavities in the bonding interface. The bonding strength initially increases with increasing HF concentration and reaches the maximum value at 2.0 ％ and then decreases. These results indicate that the 3C-SiC wafer direct bonding technique will offers significant advantages in the harsh MEMS applications.ions.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3313-3315
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• 1999

Si direct bonding(SDB) technology is very attractive for both Si-on-insulator(SOI) electric devices and MEMS applications because of its stress free structure and stability. This paper presents on pre-bonding according to HF pre-treatment conditions in Si wafer direct bonding. The characteristics of bonded sample were measured under different bonding conditions of HF concentration, and applied pressure. The bonding strength was evaluated by tensile strength method. The bonded interface and the void were analyzed by using SEM and IR camera respectively. A bond characteristic on the interface was analyzed by using IT- IR. Si-F bonds on Si surface after HF pre-treatment are replaced by Si-OH during a DI water rinse. Consequently, hydrophobic wafer was bonded by hydrogen bonding of Si $OH{\cdots}(HOH{\cdots}HOH{\cdots}HOH){\cdots}OH-Si$. The bond strength depends on the HF pre-treatment condition before pre- bonding (Min:$2.4kgf/crn^2{\sim}Max:14.9kgf/crn^2$)

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.2020-2022
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• 2002

SiC direct bonding technology is very attractive for both SiCOI(SiC-on-insulator) electric devices and SiC-MEMS fileds because of its application possibility in harsh environements. This paper presents on pre-bonding according to HF pre-treatment conditions in SiC wafer direct bonding using PECVD oxide. The PECVD oxide was characterized by XPS and AFM, respectively. The characteristics of bonded sample were measured under different bonding conditions of HF concentration and applied pressure, respectively. The bonding strength was evaluated by tensile strength method. Components existed in the interlayer were analyzed by using FT-IR. The bond strength depends on the HF pre-treatment condition before pre-bonding (Min : 5.3 kgf/$cm^2{\sim}$ Max : 15.5 kgf/$cm^2$).

• Journal of Sensor Science and Technology
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• v.16 no.5
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• pp.325-330
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• 2007

For the application to optic devices, wafer level package including spacer with particular thickness according to optical design could be required. In these cases, the uniformity of spacer thickness is important for bonding strength and optical performance. Packaging process has to be performed at low temperature in order to prevent damage to devices fabricated before packaging. And if photosensitive material is used as spacer layer, size and shape of pattern and thickness of spacer can be easily controlled. This paper presents polymer bonding using thick, uniform and patterned spacing layer of SU-8 2100 photoresist for wafer level package. SU-8, negative photoresist, can be coated uniformly by spin coater and it is cured at $95^{\circ}C$ and bonded well near the temperature. It can be bonded to silicon well, patterned with high aspect ratio and easy to form thick layer due to its high viscosity. It is also mechanically strong, chemically resistive and thermally stable. But adhesion of SU-8 to glass is poor, and in the case of forming thick layer, SU-8 layer leans from the perpendicular due to imbalance to gravity. To solve leaning problem, the wafer rotating system was introduced. Imbalance to gravity of thick layer was cancelled out through rotating wafer during curing time. And depositing additional layer of gold onto glass could improve adhesion strength of SU-8 to glass. Conclusively, we established the coating condition for forming patterned SU-8 layer with $400{\mu}m$ of thickness and 3.25 % of uniformity through single coating. Also we improved tensile strength from hundreds kPa to maximum 9.43 MPa through depositing gold layer onto glass substrate.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2005.06a
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• pp.1140-1144
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• 2005

A plastic-based CE (capillary electrophoresis) microchip was fabricated by hot embossing process. A Si mold was made by wet etching process and a PMMA wafer was cut off from 1mm thick PMMA sheet. A micro-channel structure on PMMA substrate was produced by hot embossing process using the Si mold and the PMMA wafer. A vacuum assisted thermal bonding procedure was employed to seal an imprinted PMMA wafer and a blank PMMA wafer. The results of microscopic cross sectional images showed dimensions of channels were well preserved during thermal bonding process. In our procedure, the deformation amount of bonding process was below 1%. The entire fabrication process may be very useful for plastic based microchip systems.

• Journal of Sensor Science and Technology
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• v.31 no.1
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• pp.36-40
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• 2022

High-power devices, such as LEDs and radars, inevitably generate a large amount of heat, which is the main cause of shortening lifespan, deterioration in performance, and failure of electronic devices. The embedded IC process can be a solution; however, when applied to large-area substrates (larger than 8 in), there is a limit owing to the difficulty in the process after wafer thinning. In this study, an 8-in wafer-level high-power electronic package based on the embedded IC process was implemented with temporary bonding and debonding technology using double-sided thermal release tape. Good heat-dissipation characteristics were demonstrated both theoretically and experimentally. These findings will advance the commercialization of high-power electronic packaging.

• Proceedings of the KSME Conference
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• 2001.06e
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• pp.169-174
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• 2001

This paper reports on the development of high aspect ratio structure and 3-D integrated process for MEMS-based micro gas turbines. To manufacture high aspect ratio structures, Deep Reactive Ion Etching (DRIE) process have been developed and optimized. Specially, in this study, structures with aspect ratios greater than 10 were fabricated. Also, wafer direct bonding and Infra-Red (IR) camera bonding inspection systems have been developed. Moreover, using glass/silicon wafer direct bonding, we optimized the 3-D integrated process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1998.06a
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• pp.411-414
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• 1998

In this paper, the silicon-nitride membrane structure for IR sensor was fabricated through the etching and the direct bonding. The PT layer as a IR detection layer was deposited on the membrane and its characteristics were measured. The attack of PT layer during the etching of silicon wafer as well as the thermal isolation of the IR detection layer can be solved through the method of bonding/etching of silicon wafer. Because the PT layer of c-axial orientation rained thermal polarization without polling, the more integration capability can be achieved. The surface roughness of the membrane was measured by AFM, the micro voids and the non-contacted area were inspected by IR detector, and the bonding interface was observed by SEM. The polarization characteristics and the dielectric characteristics of the PT layer were measured, too.