• Korean Journal of Materials Research
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• v.23 no.10
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• pp.580-585
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• 2013

To observe the formation of defects at the interface between an oxide semiconductor and $SiO_2$, ZnO was prepared on $SiO_2$ with various oxygen gas flow rates by RF magnetron sputtering deposition. The crystallinity of ZnO depends on the characteristic of the surface of the substrate. The crystallinity of ZnO on a Si wafer increased due to the activation of ionic interactions after an annealing process, whereas that of ZnO on $SiO_2$ changed due to the various types of defects which had formed as a result of the deposition conditions and the annealing process. To observe the chemical shift to understand of defect deformations at the interface between the ZnO and $SiO_2$, the O 1s electron spectra were convoluted into three sub-peaks by a Gaussian fitting. The O 1s electron spectra consisted of three peaks as metal oxygen (at 530.5 eV), $O^{2-}$ ions in an oxygen-deficient region (at 531.66 eV) and OH bonding (at 532.5 eV). In view of the crystallinity from the peak (103) in the XRD pattern, the metal oxygen increased with a decrease in the crystallinity. However, the low FWHM (full width at half maximum) at the (103) plane caused by the high crystallinity depended on the increment of the oxygen vacancies at 531.66 eV due to the generation of $O^{2-}$ ions in the oxygen-deficient region formed by thermal activation energy.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.3 no.3
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• pp.661-669
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• 1999

A probe card is one of the most important pan of test systems as testing IC(integrated circuit) chips. This work was related to bump-type silicon vertical probe card which enabled simultaneous tests for multiple semiconductor chips. The probe consists of silicon cantilever with bump tip. In order to obtain optimum size of the cantilever, the dimensions were determined by FEM(finite element method) analysis. The probe was fabricated by RIE(reactive ion etching), isotropic etching, and bulk-micromachining using SDB(silicon direct bonding) wafer. The optimum height of the bump of the probe detemimed by FEM simulation was 30um. The optimum thickness, width, and length of the cantilever were 20 $\mum$, 100 $\mum$,and 400 $\mum$,respectively. Contact resistance of the fabricated probe card measured at contact resistance testing was less than $2\Omega$. It was also confirmed that its life time was more than 20,000 contacts because there was no change of contact resistance after 20,000 contacts.

• Journal of Sensor Science and Technology
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• v.12 no.5
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• pp.199-204
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• 2003

This paper describes on the fabrication and characteristics of a ceramic thin-film pressure sensor based on Ta-N strain-gauges for harsh environment applications. The Ta-N thin-film strain-gauges are sputter-deposited onto a micromachined Si diaphragms with buried cavity for overpressure protectors. The proposed device takes advantages of the good mechanical properties of single-crystalline Si as diaphragms fabricated by SDB and electrochemical etch-stop technology, and in order to extend the operating temperature range, it incorporates relatively the high resistance, stability and gauge factor of Ta-N thin-films. The fabricated pressure sensor presents a low temperature coefficient of resistance, high-sensitivity, low non-linearity and excellent temperature stability. The sensitivity is $1.097-1.21\;mV/V{\codt}kgf/cm^2$ in the temperature range of $25-200^{\circ}C$ and the maximum non-linearity is 0.43%FS.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.36 no.5
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• pp.442-453
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• 2023

Tandem or multijunction solar cells (MJSCs) can convert sunlight into electricity with higher efficiency (η) than single junction solar cells (SJSCs) by dividing the solar irradiance over sub-cells having distinct bandgaps. The efficiencies of various common SJSC materials are close to the edge of their theoretical efficiency and hence there is a tremendous growing interest in utilizing the tandem/multijunction technique. Recently, III-V materials integration on a silicon substrate has been broadly investigated in the development of III-V on Si tandem solar cells. Numerous growth techniques such as heteroepitaxial growth, wafer bonding, and mechanical stacking are crucial for better understanding of high-quality III-V epitaxial layers on Si. As the choice of growth method and substrate selection can significantly impact the quality and performance of the resulting tandem cell and the terminal configuration exhibit a vital role in the overall proficiency. Parallel and Series-connected configurations have been studied, each with its advantage and disadvantages depending on the application and cell configuration. The optimization of both growth mechanisms and terminal configurations is necessary to further improve efficiency and lessen the cost of III-V on Si tandem solar cells. In this review article, we present an overview of the growth mechanisms and terminal configurations with the areas of research that are crucial for the commercialization of III-V on Si tandem solar cells.

• Current Photovoltaic Research
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• v.12 no.2
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• pp.37-40
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• 2024

One of the current innovation trends in the solar industry is the increase in the size of silicon wafers. As the wafer size increases, the series resistance of the module rises, highlighting the need for research on methods for cutting and bonding solar cells. Among these, the Infrared (IR) laser scribing technique has been extensively researched. However, there is still insufficient optimization research regarding the thermal damage caused by lasers on the Transparent Conductive Oxide (TCO) layer of Heterojunction (HJT) solar cells. Therefore, in this study, we systematically varied conditions such as IR laser scribing speed, frequency, power, and the number of scribes to investigate their impact on the performance of cut cells under each condition. Additionally, we conducted a comparative analysis of thermal damage effects on the TCO layer based on varying scribing depths.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.