• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.9
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• pp.1847-1855
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• 2012

A 1V 1.6-GS/s 6-bit flash analog-to-digital converter (ADC) with a clock calibration circuit is proposed. A single track/hold circuit with a bootstrapped analog switch is used as an input stage with a supply voltage of 1V for the high speed operation. Two preamplifier-arrays and each comparator composed of two-stage are implemented for the reduction of analog noises and high speed operation. The clock calibration circuit in the proposed flash ADC improves the dynamic performance of the entire flash ADC by optimizing the duty cycle and phase of the clock. It adjusts the reset and evaluation time of the clock for the comparator by controlling the duty cycle of the clock. The proposed 1.6-GS/s 6-bit flash ADC is fabricated in a 1V 90nm 1-poly 9-metal CMOS process. The measured SNDR is 32.8 dB for a 800 MHz analog input signal. The measured DNL and INL are +0.38/-0.37 LSB, +0.64/-0.64 LSB, respectively. The power consumption and chip area are $800{\times}500{\mu}m2$ and 193.02mW.

• Journal of Navigation and Port Research
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• v.29 no.10 s.106
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• pp.859-863
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• 2005

This paper describes the improvement of power control characteristics of ship's emergency lighting power supply(SELPS), by which electric power is controlled extensively, and power ON-OFF is controlled and system parameter monitored in remote distance by PC serial communication. Proposed system is composed of step-down converter(SDC), emergency power supply circuit(EPSC), half bridge(HB) inverter, fluorescent lamp(FL) starting circuit, microprocessor control and multi communication circuit. Experimental works confirm that relative system stops when over current is detected and speedy and stable emergency power is supplied when main power source cut-off, and controls input power up to 35[$\%$] by adjusting pulse frequency of the HB inverter, and ON-OFF control of multiple SELS, real time transmission and monitor of parameters as to voltage, current, and power values are performed appropriately by PC communication.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.9
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• pp.68-73
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• 2013

In this paper, we proposed a readout circuit of pulse waveform and rate for a U-health system to monitor health condition. For long-time operation without replacing or charging a battery, either pulse waveform or pulse rate is selected as the output data of the proposed readout circuit according to health condition of a user. The proposed readout circuit consists of a simple digital logic discriminator and a dual-mode ADC which operates in the ADC mode or in the count mode. Firstly, the readout circuit counts pulse rate for 4 seconds in the count mode using the dual-mode ADC. Health condition is examined after the counted pulse rate is accumulated for 1 minute in the discriminator. If the pulse rate is out of the preset normal range, the dual-mode ADC operates in the ADC mode where pulse waveform is converted into 10-bit digital data with the sampling frequency of 1 kHz. These data are stored in a buffer and transmitted by 620 kbps to an external monitor through a RF transmitter. The data transmission period of the RF transmitter depends on the operation mode. It is generally 1 minute in the normal situation or 1 ms in the emergency situation. The proposed readout circuit was designed with $0.11{\mu}m$ process technology. The chip area is $460{\times}800{\mu}m^2$. According to measurement, the power consumption is $161.8{\mu}W$ in the count mode and $507.3{\mu}W$ in the ADC mode with the operating voltage of 1 V.