• 대한전기학회:학술대회논문집
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• 대한전기학회 2003년도 추계학술대회 논문집 전력기술부문
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• pp.251-254
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• 2003

A voltage stability assessment consists of the contingency screening, voltage stability analysis, and counter measures. A widely used index for the voltage stability assessment of power system is the reactive power margin. It shows some factors of voluntariness as following the status of power system and load levels for the target analyzing area. Therefore, it has a demerit that the absolute amounts of reactive power margin is not to be applied by the quantized margin criterion. This paper selects a vulnerable area by assigning the voltage instability for the particular contingency for the selection of vulnerable area in the respect of the investigation of reactive power margin or VQVI as an index of V-Q margin sensitivity in order to overcome the demerit. This will be able to grasp the V-Q margin sensitivity for the target analyzing area by presenting the ratio of power margin between the margin before and after contingency as following the calculation of reactive power margin. The presented method is applied to the voltage stability assessment for the Metropolitan area of 2003 KEPCO summer peak system.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제51권11호
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• pp.541-545
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• 2002

This paper proposes the new narrow erase method to erase wall charges formed in an AC plasma display panel (PDP) cell. In the proposed method, pulse timing of switch at the sustain period is adjusted for inducing, a weak discharge. Then, after the narrow erase, the voltage of the X electrode is set to differ from that of the Y electrode. For the proposed method, the measured maximum address voltage margin was 38.3V at Y_Rest voltage of 100V and sustain voltage of 180${\sim}$185V. However, for the conventional method, in which the X and Y electrodes are set to be of equal voltage after the narrow erase, the measured maximum address voltage margin was 31.3V at Y_Rest voltage of 150V and sustain voltage of 180V. This result shows that the measured maximum voltage margin for the proposed method is about 7V(22%) higher than that for the conventional method.

• KIEE International Transactions on Power Engineering
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• 제5A권2호
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• pp.152-158
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• 2005

This paper describes a reactive optimal power flow incorporating margin enhancement constraints. Margin sensitivity at a steady-state voltage instability point is calculated using invariant space parametric sensitivity, and it can provide valuable information for selection of effective control parameters. However, the weakest buses in neighboring regions have high margin sensitivities within a certain range. Hence, the control determination using only the sensitivity information might cause violation of operational limits of the base operating point, at which the control is applied to enhance voltage stability margin in the direction of parameter increase. This paper applies an interior point method (IPM) to solve the optimal power flow formulation with the margin enhancement constraints, and shunt capacitances are mainly considered as control variables. In addition, nonlinearity of margin enhancement with respect to control of shunt capacitance is considered for speed-up control determination in the numerical example using the IEEE 118-bus test system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1993년도 하계학술대회 논문집 A
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• pp.33-35
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• 1993

This paper presents a new optimal VAR planning algorithm considering voltage stability margin. The characteristic of this method is to make it possible to formulate VAR planning for the dual purpose of maintaining voltage profiles within specified limits, and increasing the voltage stability margin of anticipated operating conditions with respect to voltage collapse. The IEEE-30 bus system is used to demonstrate the capability of the proposed algorithm.

• KIEE International Transactions on Power Engineering
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• 제4A권3호
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• pp.141-145
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• 2004

FACTS devices, such as the Thyristor Controlled Series Compensator (TCSC) and Static Var Compensators (SVC), can help increase system load margin to improve static voltage stability. In power systems, because of the high cost and the effect value, the optimal placement for FACTS devices must be determined. This paper investigates the use of the series device (SVC) and the parallel device (TCSC) from the point of load margin to increase voltage stability. It considers the sensitivity of load margin to the line reactance and eigenvector of the collapse. The study has been carried out on the IEEE 14 Bus Test System to verify the validity and efficiency of the method. It reveals that incorporation of FACTS devices significantly enhance load margin as well as system stability.

• 전기학회논문지P
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• 제66권4호
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• pp.206-212
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• 2017

In this paper, using the power system information obtained from real-time monitoring device, to analyze the voltage stability margin index and described the voltage stability control scheme for voltage stability enhancement. Based on the utilization of the voltage stability monitoring index based on local information provided by the PMU(Phasor Measurement Unit), the purpose of the plan is to control the system stably in real time. In order to apply the load control scheme, the voltage stability margin is calculated using the data acquired through the PMU installed in each load bus. If the voltage drops below a certain level, load control is performed for each. The effectiveness of the voltage stability control measures is applied to the actual KEPCO system to analyze the effectiveness.

• 대한전기학회논문지:전력기술부문A
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• 제48권4호
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• pp.351-357
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• 1999

This paper proposes the coordinated control of SVC and UTLC at the distribution substation to get larger operating margin of SVC for the voltage stability control by reactive power compensation. In the conventional method, ULTC doesn't respond to the variation of source voltage, so SVC has the entire responsibility for it. It could cause the lack of operating margin of SVC in some condition. It, however, is important to secure an operating margin for the dynamic stability control in emergancy. This paper proposes the coordinated control method that SVC controls the supply voltage and ULTC respond to the SVC compensation valve based on the relation between SVC compensation and ULTC tap position. The numerical simulation verifies that the proposed system could increase the operating margin of SVC compared with the conventional system.

• 전기학회논문지P
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• 제63권1호
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• pp.1-6
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• 2014

An electric power system sometimes fails because of disturbances that occur unexpectedly, such as the uncontrolled loss of load that developed from cascading blackout. Which make stability through a little of under voltage load shedding should work. The development of phasor measurement unit(PMU) makes network supervision possible. The information obtained from PMU is synchronized by global positioning system(GPS). There are many real-time algorithms which are monitoring the voltage stability. This paper presents the study on the VILS(Voltage Instability Load Shedding) using PMU data. This algorithm computes Voltage Stability Margin Index(VSMI) continuously to track the voltage stability margin at local bus level. The VSMI is expressed as active and reactive power. The VSMI is used as an criterion for load shedding. In order to examine the algorithm is effective, applied to KEPCO system.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 학술대회 논문집 정보 및 제어부문
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• pp.460-461
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• 2008

A new AC-PDP driving method was proposed to reduce the address period. The overlapped scan method can reduce the address period. However, this method has a narrow address voltage margin compared with conventional scan method in this paper, Slope overlapped scan method is presented. The proposed new overlapped scan method allows wider address voltage margin than conventional overlapped scan method.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권2호
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• pp.118-129
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• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.