• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.469-478
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• 2001

In the virtual memory system, page replacement policy exerts a great influence on the performance of demand paging. There are LRU(Least Recently Used) and LFU (Least Frequently Used) as the typical replacement policies. The LRU policy performs effectively in many cases and adapts well to the changing workloads compared to other policies. It however cannot distinguish well between frequently and infrequently referenced pages. The LFU policy requires that the page with the smallest reference count be replaced. Though it considers all the references in the past, it cannot discriminate between references that occurred far back in the past and the more recent ones. Thus, it cannot adapt well to the changing workload. In this paper, we first analyze memory reference patterns of eight applications. The patterns show that the recently referenced pages or the frequently referenced pages are accessed continuously as the case may be. So it is rather hard to optimize page replacement scheme by using just one of the LRU or LFU policy. This paper makes an attempt to combine the advantages of the two policies and proposes a new page replacement policy. In the proposed policy, paging list is divided into two lists (LRU and LFU lists). By keeping the two lists in recency and reference frequency order respectively, we try to restrain the highly referenced pages in the past from being replaced by the LRU policy. Results from trace-driven simulations show that there exists points on the spectrum at which the proposed policy performs better than the previously known policies for the workloads we considered. Especially, we can see that our policy outperforms the existing ones in such applications that have reference patterns of re-accessing the frequently referenced pages in the past after some time.

• The KIPS Transactions:PartB
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• v.10B no.7
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• pp.795-802
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• 2003

To live autonomously, intelligent agents such as robots or virtual characters need ability that recognizes given environment, and learns and chooses adaptive actions. So, we propose an action selection/learning mechanism in intelligent agents. The proposed mechanism employs a hybrid system which integrates a behavior-based method using the reinforcement learning and a cognitive-based method using the symbolic learning. The characteristics of our mechanism are as follows. First, because it learns adaptive actions about environment using reinforcement learning, our agents have flexibility about environmental changes. Second, because it learns environmental factors for the agent's goals using inductive machine learning and association rules, the agent learns and selects appropriate actions faster in given surrounding and more efficiently in extended surroundings. Third, in implementing the intelligent agents, we considers only the recognized states which are found by a state detector rather than by all states. Because this method consider only necessary states, we can reduce the space of memory. And because it represents and processes new states dynamically, we can cope with the change of environment spontaneously.

• Journal of Internet Computing and Services
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• v.12 no.5
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• pp.63-72
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• 2011

Binary translation is a kind of the emulation method which converts a binary code compiled on the particular instruction set architecture to the new binary code that can be run on another one. It has been mostly used for migrating legacy systems to new architecture. In recent, binary translation is used for instrumenting programs without modifying source code, because it enables inserting additional codes dynamically, For general application, there already exists some instrumentation software using binary translation, such as dynamic binary analyzers and virtual machine monitors. On the other hand, in order to be benefited from binary translation in kernel-level, a few issues, which include system performance, memory management, privileged instructions, and synchronization, should be treated. These matters are derived from the structure of the kernel, and the difference between the kernel and user-level application. In this paper, we present a scheme to apply binary translation and dynamic instrumentation on kernel. We implement it on Linux kernel and demonstrate that kernel-level binary translation adds an insignificant overhead to performance of the system.

• Journal of Korea Multimedia Society
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• v.10 no.8
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• pp.1060-1067
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• 2007

We need various methods to develop MMORPG that is game genre which many users use among various game genre using Internet. Specially, to heighten efficiency of distributing work, Object-oriented language such as C++ is used and we need design techniques that can take advantage of enough object-oriented concept when making large-scale game. There is various pattern that can apply in software breakup design in GoF's design pattern for these design techniques. If you apply Observer pattern to Party System Design for forming community between game users, you can easily add new class and maintain system later. Party Play is one of the important system that is used to form game users' community in MMORPG games. The main point that must be considered in Party-Play-System is to divide evenly experience value and acquisition that is got by Party-Play among users according to each user's level. To implement Party Play System that consider maintenance of system, in this paper, we propose a method using GoF's Observer-Pattern, showing you that proposed method which has advantage to dynamic memory allocation and to virtual method call can be used usefully to change object to real time at program run and to add new class and to maintain system new.

• The Transactions of the Korea Information Processing Society
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• v.3 no.7
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• pp.1669-1679
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• 1996

In this paper, we address the problem of how to replace huffers in multimedia database systems with time-varying skewed data access. The access pattern in the multimedia database system to support audio-on-demand and video-on-demand services is generally skewed with a few popular objects. In addition the access pattem of the skewed objects has a time-varying property. In such situations, our analysis indicates that conventional LRU(least Recently Used) and LFU(Least Frequently Used) schemes for buffer replacement algorithm(ABRN:Adaptive Buffer Replacement using Neural suited. We propose a new buffer replacement algorithm(ABRN:Adaptive Buffer Replacement using Neural Networks)using a neural network for multimedia database systems with time-varying skewed data access. The major role of our neural network classifies multimedia objects into two classes:a hot set frequently accessed with great popularity and a cold set randomly accessed with low populsrity. For the classification, the inter-arrival time values of sample objects are employed to train the neural network.Our algorithm partitions buffers into two regions to combine the best roperties of LRU and LFU.One region, which contains the 핫셋 objects, is managed by LFU replacement and the other region , which contains the cold set objects , is managed by LRUreplacement.We performed simulation experiments in an actual environment with time-varying skewed data accsee to compare our algorithm to LRU, LFU, and LRU-k which is a variation of LRU. Simulation resuults indicate that our proposed algorthm provides better performance as compared to the other algorithms. Good performance of the neural network-based replacement scheme means that this new approach can be also suited as an alternative to the existing page replacement and prefetching algorithms in virtual memory systems.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.8
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• pp.868-872
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• 2010

Many embedded Java systems are equipped with limited memory, which can constrain the code cache size provided for Java just-in-time compilation, affecting the Java performance. This paper proposes expanding the limited code cache when it is full, by saving the machine code for some methods in the code cache into the file system of the permanent storage and reloading it to the code cache when they are re-invoked later. This is applying the client ahead-of-time compilation during the execution time for the purpose of enlarging the code cache. Our experimental results indicate that the proposed execution method can improve the performance by as much as 1.6 times compared to the conventional method, when the code cache size is reduced by half.

• The Journal of the Korea Contents Association
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• v.17 no.3
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• pp.370-381
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• 2017

Recently, a complex event processing system has been introduced to quickly and efficiently process real-time events in various applications. Since the existing complex event processing schemes do not consider the similarity and duplication of operators, they perform a lot of computations and consume memory. To solve such problems, this paper proposes an efficient complex event processing scheme considering similar operators and duplication operations. When the same primitive events have similar operations, the proposed scheme combines them into one virtual operator. For duplicated operations, the proposed scheme processes only one of them first, and then processes the others using the results of the already processed operation when the same operation is subsequently performed. It is shown through performance comparison that the proposed scheme outperforms the existing scheme in terms of the whole operation throughput.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.5
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• pp.49-54
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• 2022

With the recent widespread adoption of general-purpose GPUs (GPGPUs) in cloud systems, maximizing the resource utilization through multitasking in GPGPU has become an important issue. In this article, we show that resource allocation based on the workload classification of computing-bound and memory-bound is not sufficient with respect to resource utilization, and present a new thread block scheduling policy for GPGPU that makes use of fine-grained resource utilizations of each workload. Unlike previous approaches, the proposed policy reduces scheduling overhead by separating profiling and scheduling, and maximizes resource utilizations by co-locating workloads with different bottleneck resources. Through simulations under various virtual machine scenarios, we show that the proposed policy improves the GPGPU throughput by 130.6% on average and up to 161.4%.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.33 no.1
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• pp.87-97
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• 2023

Containers are an emerging virtualization technology that can build an isolated environment more lightweight and faster than existing virtual machines. For that reason, many organizations have recently adopted them for their services. Yet, the container architecture has also exposed many security problems since all containers share the same OS kernel. In this work, we focus on the fact that an attacker can abuse host resources to make them unavailable to benign containers-also known as host resource exhaustion attacks. Then, we analyze the impact of host resource exhaustion attacks through real attack scenarios exhausting critical host resources, such as CPU, memory, disk space, process ID, and sockets in Docker, the most popular container platform. We propose five attack scenarios performed in several different host environments and container images. The result shows that three of them put other containers in denial of service.

• Journal of Korea Multimedia Society
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• v.3 no.5
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• pp.526-534
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• 2000

There have been many researches on the 3D graphic accelerator for high speed by needs of CAD/CAM,3D modeling, virtual reality or medical image. In this paper, an SIMD processor architecture for 3D graphic accelerator is proposed in order to improve the processing time of the 3D graphics, and a parallel Phong shading algorithm is presented to estimate performance of the proposed architecture. The proposed SIMD processor architecture for 3D graphic accelerator consists of PCI local bus interface, 16 Processing Elements (PE's), and Park's multi-access memory system (NAMS) that has 17 memory modules. A serial algorithm for Phong shading is modified for the architecture and the main key is to divide a polygon into $4\times{4}$ squares. And, for processing a square, 4 PE's are regarded as a PE Grou logically. Since MAMS can support block access type with interval 1, it is possible that 4 PE Groups process a square at a time. In consequence, 16 pixels are processed simultaneously. The proposed SIMD processor architecture is simulated by CADENCE Verilog-XL that is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed enhancement by the parallel algorithm to the serial one is 5.68.