• Title/Summary/Keyword: virtual block

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Development of a SMS Moodle Block (SMS 무들 블록 개발)

  • Park, Jong-Dae;Jang, Jin-Hoon
    • The Journal of Natural Sciences
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    • v.19 no.1
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    • pp.1-10
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    • 2008
  • A SMS Moodle plug-in block was developed for the Pai-Chai Moodle virtual learning environment. Professors can send SMS messages directly from their courses by using the SMS block. NuSOAP open source web service library was utilized for XML SOAP based message transfer.

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Cubical User Interface for Toy Block Composition in Augmented Reality (증강 현실에서의 장난감 블록 결합을 위한 큐브형 사용자 인터페이스)

  • Lee, Hyeong-Mook;Lee, Young-Ho;Woo, Woon-Tack
    • 한국HCI학회:학술대회논문집
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    • 2009.02a
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    • pp.363-367
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    • 2009
  • We propose Cubical User Interface(CUI) for toy block composition in Augmented Reality. The creation of new object by composing virtual object is able to construct various AR contents effectively. However, existing GUI method requires learning time or is lacking of intuitiveness between act of user and offered interface. In case of AR interfaces, they mainly have been supported one handed operation and it did not consider composition property well. Therefore, the CUI provide tangible cube as the manipulation tool for virtual toy block composition in AR. The tangible cube which is attached multi-markers, magnets, and buttons supports free rotation, combination, and button input. Also, we propose two kinds of two-handed composing interactions based on CUI. First is Screw Driving(SD) method which is possible to free 3-D positioning and second is Block Assembly(BA) method which support visual guidance and is fast and intuitive. We expected that proposed interface can apply as the authoring system for content such as education, entertainment, Digilogbook.

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A Cache Management Technique for an Efficient Video Proxy Server (효율적인 비디오 프록시 서버를 위한 캐시 관리 방법)

  • Lee, Jun-Pyo;Park, Sung-Han
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.46 no.4
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    • pp.82-88
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    • 2009
  • Video proxy server which is located near clients can store the frequently requested video data in storage space in order to minimize initial latency and network traffic significantly. However, due to the limited storage space in video proxy server, an appropriate video selection method is needed to store the videos which are frequently requested by users. Thus, we present a virtual caching technique to efficiently store the video in video proxy server. For this purpose, we employ a virtual memory in video poky server. If the video is requested by user, it is loaded in virtual memory first and then, delivered to the user. A video which is loaded in virtual memory is deleted or moved into the storage space of video poxy sewer depending on the request condition. In addition, virtual memory is divided into each segment area in order to store the segments efficiently and to avoid the fragmentation. The simulation results show that the proposed method performs better than other methods in terms of the block hit rate and the number of block deletion.

Stereo-To-Multiview Conversion System Using FPGA and GPU Device (FPGA와 GPU를 이용한 스테레오/다시점 변환 시스템)

  • Shin, Hong-Chang;Lee, Jinwhan;Lee, Gwangsoon;Hur, Namho
    • Journal of Broadcast Engineering
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    • v.19 no.5
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    • pp.616-626
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    • 2014
  • In this paper, we introduce a real-time stereo-to-multiview conversion system using FPGA and GPU. The system is based on two different devices so that it consists of two major blocks. The first block is a disparity estimation block that is implemented on FPGA. In this block, each disparity map of stereoscopic video is estimated by DP(dynamic programming)-based stereo matching. And then the estimated disparity maps are refined by post-processing. The refined disparity map is transferred to the GPU device through USB 3.0 and PCI-express interfaces. Stereoscopic video is also transferred to the GPU device. These data are used to render arbitrary number of virtual views in next block. In the second block, disparity-based view interpolation is performed to generate virtual multi-view video. As a final step, all generated views have to be re-arranged into a single image at full resolution for presenting on the target autostereoscopic 3D display. All these steps of the second block are performed in parallel on the GPU device.

A Novel Fast Open-loop Phase Locking Scheme Based on Synchronous Reference Frame for Three-phase Non-ideal Power Grids

  • Xiong, Liansong;Zhuo, Fang;Wang, Feng;Liu, Xiaokang;Zhu, Minghua;Yi, Hao
    • Journal of Power Electronics
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    • v.16 no.4
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    • pp.1513-1525
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    • 2016
  • Rapid and accurate phase synchronization is critical for the reliable control of grid-tied inverters. However, the commonly used software phase-locked loop methods do not always satisfy the need for high-speed and accurate phase synchronization under severe grid imbalance conditions. To address this problem, this study develops a novel open-loop phase locking scheme based on a synchronous reference frame. The proposed scheme is characterized by remarkable response speed, high accuracy, and easy implementation. It comprises three functional cascaded blocks: fast orthogonal signal generation block, fast fundamental-frequency positive sequence component construction block, and fast phase calculation block. The developed virtual orthogonal signal generation method in the first block, which is characterized by noise immunity and high accuracy, can effectively avoid approximation errors and noise amplification in a wide range of sampling frequencies. In the second block, which is the foundation for achieving fast phase synchronization within 3 ms, the fundamental-frequency positive sequence components of unsymmetrical grid voltages can be achieved with the developed orthogonal signal construction strategy and the symmetrical component method. The real-time grid phase can be consequently obtained in the third block, which is free from self-tuning closed-loop control and thus improves the dynamic performance of the proposed scheme. The proposed scheme is adaptive to severe unsymmetrical grid voltages with sudden changes in magnitude, phase, and/or frequency. Moreover, this scheme is able to eliminate phase errors induced by harmonics and random noise. The validity and utility of the proposed scheme are verified by the experimental results.

ATM Interface Technologies for an ATM Switching System

  • Park, Hong-Shik;Kwon, Yool;Kim, Young-Sup;Kang, Seok-Youl
    • ETRI Journal
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    • v.18 no.4
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    • pp.229-244
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    • 1997
  • Realization of the economical, reliable, and efficient ATM interface block becomes an important key to development of the ATM switching system when we consider new issues raised recently. In this paper, we summarize requirements for the ATM interface block and present the UNI (User Network Interface)/NNI (Network Node Interface) architecture to meet these requirements. We also evaluate the performance of the multiplexer adopting the various multiplexing schemes and service disciplines. For ATM UNI/NNI interface technologies, we have developed a new policing device using the priority encoding scheme. It can reduce the decision time for policing significantly. We have also designed a new spacer that can space out the clumped cell stream almost perfectly. This algorithm guarantees more than 99 % conformance to the negotiated peak cell rate. Finally, we propose the interface architecture for accommodation of the ABR (Available Bit Rate) transfer capability. The proposed structure that performs virtual source and virtual destination functions as well as a switch algorithm can efficiently accommodate the ABR service.

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New channel estimation algorithm for W-CDMA reverse link using pilot symbols over fast Rayleigh-fading multipath channels

  • Koo, Je-Gil;Park, Hyung-Jin
    • Proceedings of the IEEK Conference
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    • 2000.07b
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    • pp.982-985
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    • 2000
  • This paper presents channel estimation of an asynchronous W-CDMA reverse link using the interpolation and moving average algorithm in frequency-selective Rayleigh fading channel. The proposed algorithm is an interpolated decision-directed (IDD) block-wise moving average (BWMA) algorithm. The IDD-BWMA algorithm performs two- stage processes. The first stage performs data decision to make a virtual pilot channel by using linear interpolation channel estimation scheme. Then, the second stage performs the channel estimation of the “block-wise moving average” type by using a virtual pilot channel obtained in the first stage. By using Monte-Carlo computer simulations, we show that the proposed channel estimator is superior to other estimation schemes such as the WMSA(K=1) and DD-RAKE at higher Doppler frequencies, especially.

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Guitar Tab Digit Recognition and Play using Prototype based Classification

  • Baek, Byung-Hyun;Lee, Hyun-Jong;Hwang, Doosung
    • Journal of the Korea Society of Computer and Information
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    • v.21 no.9
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    • pp.19-25
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    • 2016
  • This paper is to recognize and play tab chords from guitar musical sheets. The musical chord area of an input image is segmented by changing the image in saturation and applying the Grabcut algorithm. Based on a template matching, our approach detects tab starting sections on a segmented musical area. The virtual block method is introduced to search blanks over chord lines and extract tab fret segments, which doesn't cause the computation loss to remove tab lines. In the experimental tests, the prototype based classification outperforms Bayesian method and the nearest neighbor rule with the whole set of training data and its performance is similar to that of the support vector machine. The experimental result shows that the prediction rate is about 99.0% and the number of selected prototypes is below 3.0%.

Modeling and Simulation of Ship Panel-block Assembly Line Using Petri Nets (Petri Nets을 이용한 조선소 패널 블록 조립 라인의 모델링과 시뮬레이션)

  • Han, Sang-Dong;Ryu, Cheol-Ho;Shin, Jong-Gye;Lee, Jong-Kun
    • Korean Journal of Computational Design and Engineering
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    • v.13 no.1
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    • pp.36-44
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    • 2008
  • This paper proposes a modeling and simulation process of a panel production line (PPL) in a shipyard. The panel production line is an assembly process to produce a main panel of a flat block and a curved block. In this paper, its activity analysis is carried out using expression of IDEF0, and its process is qualitatively and quantitatively analyzed and modeled by Petri Nets. A commercial discrete event simulation tool, $QUEST^{TM}$, is used for virtual PPL and simulation. The modeling results by Petri Net are mapped to elements of the simulation tool. Finally, an integrated simulation environment of PPL is implemented in order to efficiently utilize the virtual PPL model. With the help of IDEF0 and Petri Nets, we could systematically analyze and describe the PPL process that are characterized as being concurrent, asynchronous, distributed, parallel, nondeterministic, and/or stochastic. Also, the dynamic and concurrent activities of a PPL system were able to be simulated. A timing concept can be included into the Petri nets model to evaluate performance and dependability issues of the system.

Improving the Read Performance of OneNAND Flash Memory using Virtual I/O Segment (가상 I/O 세그먼트를 이용한 OneNAND 플래시 메모리의 읽기 성능 향상 기법)

  • Hyun, Seung-Hwan;Koh, Kern
    • Journal of KIISE:Computing Practices and Letters
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    • v.14 no.7
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    • pp.636-645
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    • 2008
  • OneNAND flash is a high-performance hybrid flash memory that combines the advantages of both NAND flash and NOR flash. OneNAND flash has not only all virtues of NAND flash but also greatly enhanced read performance which is considered as a downside of NAND flash. As a result, it is widely used in mobile applications such as mobile phones, digital cameras, PMP, and portable game players. However, most of the general purpose operating systems, such as Linux, can not exploit the read performance of OneNAND flash because of the restrictions imposed by their virtual memory system and block I/O architecture. In order to solve that problem, we suggest a new approach called virtual I/O segment. By using virtual I/O segment, the superior read performance of OneNAND flash can be exploited without modifying the existing block I/O architecture and MTD subsystem. Experiments by implementations show that this approach can reduce read latency of OneNAND flash as much as 54%.