• Journal of Broadcast Engineering
• /
• v.19 no.5
• /
• pp.590-605
• /
• 2014

The purpose of this paper is to propose a service system for a digital hologram video, which has not been published yet. This system assumes the existing service framework for 2-dimensional or 3-dimensional image/video, which includes data acquisition, processing, transmission, reception, and reconstruction. This system includes acquisition of color and depth image pairs from a image acquisition system with vertical rigs, rectification of acquired image pairs and generating digital hologram. Also it is designed to reduce the CGH (computer-generated hologram) generation time to 1/3. It also includes some additional and optional functions such as watermarking, compression, and encryption.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.48 no.1
• /
• pp.132-140
• /
• 2011

Ultra-High Definition Television (U-HDTV) is a promising candidate for the next generation television. Since the U-HDTV video signal requires a huge amount of data, parallel implementation of the U-HDTV compression system is highly demanding. In the conventional parallel video codec, a video is divided into sub-sequences and the sub-sequences are independently encoded. In this paper, for efficient parallel processing, we propose a pipelined encoding structure which exploits cross-correlation among the sub-sequences. The experimental results demonstrate that the proposed technique improves the coding efficiency and provides the sub-sequences of the balanced visual quality.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.9
• /
• pp.2053-2061
• /
• 1997

The motion comensated video coding technology is very improtant to compress video signal since it reduces the temporal redundancies in successive frames. But the computational complexity of the motion estimation(ME) is too enormous to use in the area of real-time and/or resolution video processing applications. To reduce the complexity of ME, fast search algoritjms and hardware design methods are developed. Especially, the three step search(TSS) is well known method which shows stable performance in various video sequences. And other variations of TSS are developed to get better performance andto reduce the complexity. In this paepr, we present the modified TSS using neighboring block's motion vectors to determine first step motion vector in TSS. The presented method uses the correlation of the adjacent blocks with same motion field. The simualtion resutls show that it has a good MAE performance and low complexity comparing with original TSS.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.297-300
• /
• 2002

In this paper, we propose a post-processing method to reduce the blocking artifacts. We perform the post-processing only in the spatial domain so that it is readily applicable to real-time video decoder. Many approaches proposed so far for deblocking deal with only The luminance signal. but here we propose processing the chrominance signals as well since the low bit rare application where the blocking artifacts are most problematic suffers significantly from the color misalignment caused by blocking artifacts occurring to chrominance data as well. The proposed method is composed of low pass filtering in two steps considering the edge direction. The first step is the IIR low pass filtering in the diagonal direction, and the second step is another IIR low pass filtering in horizontal and vertical directions.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.42 no.1
• /
• pp.95-100
• /
• 2005

This paper proposes a DVS method which effectively reduces the power consumption of multimedia signal processor. Analytic derivations of effective range of its power saving factor are obtained with the assumption of a Gaussian distribution for the frame-based computational burden of the multimedia processor. A closed form equation of the power saving factor is derived in terms of the mean-standard deviation of the distribution. An MPEG-2 video decoder algorithm and AAC encoder algorithm are tested on ARM9 RISC processor for the experimental verification of the power saying of the proposed DVS approach. The experimental results with diverse MPEG-2 video and audio files show 50～30% power saving factor and show good agreement with those of the analytically derived values.

• IEIE Transactions on Smart Processing and Computing
• /
• v.2 no.6
• /
• pp.345-349
• /
• 2013

This paper proposes a simplified generalized residual prediction (GRP) that reduces the computational complexity of spatial scalability in scalable high efficiency video coding (SHVC). GRP is a coding tool to improve the inter prediction by adding a residual signal to the inter predictor. The residual signal was created by carrying out motion compensation (MC) of both the enhancement layer (EL) and up-sampled reference layer (RL) with the motion vector (MV) of the EL. In the MC process, interpolation of the EL and the up-sampled RL are required when the MV of the EL has sub-pel accuracy. Because the up-sampled RL has few high frequency components, interpolation of the up-sampled RL does not give significantly new information. Therefore, the proposed method reduces the computational complexity of the GRP by skipping the interpolation of the up-sampled RL. The experiment on SHVC software (SHM-2.0) showed that the proposed method reduces the decoding time by 10 % compared to conventional GRP. The BD-rate loss of the proposed method was as low as 1.0% on the top of SHM-2.0.

• Proceedings of the Acoustical Society of Korea Conference
• /
• autumn
• /
• pp.173-176
• /
• 1999

In this work, a A/D converter is implemented to obtain 8bit resolution at a conversion rate of 10Msample/s for video applications. Proposed architecture is designed low power A/D converter that pipelined architecture consists of flash A/D converter. This architecture consists of two identical stages that consist of sample/hold circuit, low power comparator, voltage reference circuit and MDAC of binary weighted capacitor array. Proposed A/D converter is designed using $0.25{\mu}m$ CMOS technology The SNR is 76.3dB at a sampling rate of 10MHz with 3.9MHz sine input signal. When an 8bit 10Msample/s A/D converter is simulated, the Differential Nonlinearity / Integral Nonlinearity (DNL/ INL) error are ${\pm}0.5/{\pm}2$ LSB, respectively. The power consumption is 13mW at 10Msample/s.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.12C
• /
• pp.727-737
• /
• 2011

This paper presents an implementation scheme of real-time lane and vehicle detection system with FPGA and DSP. In this type of implementation, defining the functionality of each device in efficient manner is of crucial importance. The FPGA is in charge of extracting features from input image sequences in reduced form, and the features are provided to the DSP so that tracking lanes and vehicles are performed based on them. In addition, a way of seamless interconnection between those devices is presented. The experimental results show that the system is able to process at least 15 frames per second for video image sequences with size of $640{\times}480$.

• 한국정보통신설비학회:학술대회논문집
• /
• 2009.08a
• /
• pp.131-135
• /
• 2009

This paper is the introduction of our work on distributed load scheduling in single-level tree network. In this paper, we derive a new calculation model in single-level tree network and show a closed-form formulation of the time for computation system. There are so many examples of the application of this technology such as distributed database, biology computation on genus, grid computing, numerical computing, video and audio signal processing, etc.

• Proceedings of the IEEK Conference
• /
• 1999.11a
• /
• pp.491-494
• /
• 1999

Introduction of digital communication network such as Integrated Services Digital Networks(ISDN) and digital storage media have rapidly developed. Due to a large amount of image data, compression is the key techniques in still image and video using digital signal processing for transmitting and storing. Digital image compression provides solutions for various image applications that represent digital image requiring a large amount of data. In this paper, the proposed DWT(Discrete Wavelet Transform) filter bank is consisted of simple architecture, but it is efficiently designed that a user obtain a wanted compression rate as only input parameter. If it is implemented by FPGA chip, the designed encoder operates in 12MHz.