• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.802-805
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• 2007

A hardware architecture is presented of a wavelet based multiple line addressing driving scheme for passive matrix displays using the FPGA (Field Programmable Gate Arrays), which will be integrated in the scalable video coding $architecture^{[1]}$. The incoming compressed video data stream will then directly be transformed to the required column voltages by the hardware architecture without the need of employing the video decompression.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2498-2511
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• 1997

Due to the recent advances in computer technologies and high-speed networks, telecommunication services and provision of multimedia services will be considered a new software architecture adapting networking infrastructure on information networking architecture. In this paper, the video conference services has been selected as a target service example because it is expected to become one of the most important services on the full service network. In fact, it can be viewed as the basis for providing telecommunication services such as video telephony and video conferencing. This paepr presents the prototyping of TINA(Telecommunication Information Networking Architecture) based desktop video conference system using the concepts of session management. The prototyping of deskop video conference system aims at assessing TINA concepts and refinement of the mapping between session graph and connection graph, and provides support of open service platform towards distribution and objected-orientation.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.31-43
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• 1999

The main goal of this paper is to design a high performance SVP(Stack based Video Processor) for network applications. The SVP is a comprehensive scheme; 'better' in the sense that it is an optimal selection of previously proposed enhancements of a stack machine and a video processor. This can process effectively object-based video data using a S-RISC(Stack-based Reduced Instruction Set Computer) with a semi -general-purpose architecture having a stack buffer for OOP(Object-Oriented Programming) with many small procedures at running programs. And it includes a vector processor that can improve the MPEG coding speed. The vector processor in the SVP can execute advanced mode motion compensation, motion prediction by half pixel and SA-DCT(Shape Adaptive-Discrete Cosine Transform) of MPEG-4. Absolutors and halfers in the vector processor make this architecture extensive to a encoder. We also designed a VLSI stack-oriented video processor using the proposed architecture of stack-oriented video decoding. It was designed with O.5$\mu\textrm{m}$ 3LM standard-cell technology, and has 110K logic gates and 12 Kbits SRAM internal buffer. The operating frequency is 50MHz. This executes algorithms of video decoding for QCIF 15fps(frame per second), maximum rate of VLBV(Very Low Bitrate Video) in MPEG-4.

• Journal of Electrical Engineering and information Science
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• v.2 no.5
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• pp.9-16
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• 1997

This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals, It also processes he PAL-plus video signal which is now popular in Europe. The encoder consists of five major building functions which are letter-box converter, color space converter, digital filters, color modulator and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance signal-to-noise ratio of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs re luminance(Y), chrominance(C), and composite video baseband(Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Veriflog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 42K gates and is implemented by using 0.6um CMOS process.

• Proceedings of the KSRS Conference
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• 2002.10a
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• pp.117-122
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• 2002

In this paper, we propose Media GIS web service architecture using 3D geographical database and GPS-related data resulted from 4S-Van. We introduce a novel interoperable geographical data service concept; so-called, Virtual World Mapping (VWM) that can map 3D graphic world with real-world video. Our proposed method can easily retrieve geographical in-formation and attributes to reconstruct 3D virtual space according to certain frame in video sequences. Our proposed system architecture also has an advantage that can provide geographical information service with video stream without any image processing procedures. In addition to, describing the details of our components, we present a Media GIS web service system by using GeoVideo Server, which performs VWM technique.

• Korean Journal of Remote Sensing
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• v.19 no.1
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• pp.71-80
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• 2003

In this Paper, we Propose web-based Media GIS architecture using 3D geographical database and GPS-related data resulted from 45-Van. We introduce a novel interoperable geographical data service concept; so-called, Virtual World Mapping (VWM) that can map 3D graphic world with real-world video. Our proposed method can easily retrieve geographical information and attributes to reconstruct 3D virtual space according to certain frame in video sequences. Our proposed system architecture also has an advantage that can provide geographical information service with video stream without any image processing procedures. In addition to, describing the details of our components, we present a Media GIS web service system by using GeoVideoServer, which performs VWM technique.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.229-234
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• 2007

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

• The Transactions of the Korea Information Processing Society
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• v.4 no.12
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• pp.3097-3110
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• 1997

As to the recent advances in computer technologies and high-speed networks, telecommunication services and provision of multimedia services will be provided on the basic of a new software architecture adapting networking infrastructure on open information networking architecture. In this paper, the video conference services has been selected as a target service example because it is expected to become one of the most important services on the full service network. In fact, it can be viewed as the basis for providing telecommunication services such as video telephony and video conferencing. This paper presents the prototyping of TINA (Telecommunication Information Networking Architecture) based desktop video conference system using the concepts of session management. The prototyping of desktop video conference system aims at assessing TINA concepts and refinement of the mapping between session graph and connection graph, and provides object modeling methodologies towards distribution and objected-orientation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.11A
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• pp.1098-1103
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• 2005

The edge and contour information are very much appreciated by the human visual systems and are responsible for our perceptions and recognitions. Therefore, if edge information is integrated during extracting video objects, we can generate boundaries of oects closer to human visual systems for multimedia applications such as interaction between video objects, object-based coding, and representation. Most of object extraction methods are difficult to implement real-time systems due to their iterative and complex arithmetic operations. In this paper, we propose a VLSI architecture integrating edge information to extract video objects for precisely located object boundaries. The proposed architecture can be easily implemented into hardware due to simple arithmetic operations. Also, it can be applied to real-time object extraction for object-oriented multimedia applications.