• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.584-587
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• 2008

In this paper, we propose a real time video codec adapter for enabling video communications with terminals having a codec which is different from each other. When multimedia services are playing with an office service phone such as a video phone or software phone which has video capability, each terminal is not being considered to have optimized video or voice codec. So when a video phone with only one type of video codec is used in the video streaming service which requires another type of codec, the streaming service is not successful without codec transformation. The real time codec adapter in this paper provides a real time code transformation which enables communication services such as video conferencing between terminals which have different codec.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.6
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• pp.434-442
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• 2015

In this paper, we propose an integrated spatial and view scalable video codec based on high efficiency video coding (HEVC). The proposed video codec is developed based on similarity and uniqueness between the scalable extension and 3D multi-view extension of HEVC. To improve compression efficiency using the proposed scalable multi-view video codec, inter-layer and inter-view predictions are jointly employed by using high-level syntaxes that are defined to identify view and layer information. For the inter-view and inter-layer predictions, a decoded picture buffer (DPB) management algorithm is also proposed. The inter-view and inter-layer motion predictions are integrated into a consolidated prediction by harmonizing with the temporal motion prediction of HEVC. We found that the proposed scalable multi-view codec achieves bitrate reduction of 36.1%, 31.6% and 15.8% on the top of ${\times}2$, ${\times}1.5$ parallel scalable codec and parallel multi-view codec, respectively.

• Journal of Broadcast Engineering
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• v.21 no.2
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• pp.219-236
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• 2016

In this paper, we design and implement a 3D scalable video codec by combining the Scalable HEVC (SHVC) and the 3D-HEVC which are the extended standards of High Efficiency Video Coding (HEVC). The proposed 3D scalable video codec supports the view and spatial scalabilities which are the properties of 3D-HEVC and SHVC, respectively. In the proposed 3D scalable codec, the high-level syntaxes are designed to support the multiple scalabilities. In the computer simulation section, we confirmed the conformance of the proposed codec and analyzed the performance of the proposed codec.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1308-1311
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• 2002

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in wireless multimedia applications. The discussion will focus on the architectural design techniques for implementing a high-performance video compression/decompression chip at low power architectures. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz for 128k∼144kbps. By introducing the efficiently optimized Frame Memory Interface architecture, low power motion estimation and embedded ARM microprocessor and AMBA interface, the proposed MPEG-4 video codec has low power consumption for wireless multimedia applications such as IMT-2000.

• ETRI Journal
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• v.27 no.5
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.06a
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• pp.37-42
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• 1997

This paper describes two different S/W-based video codec systems. One is a frame-based video codec with fixed structure based on ITU H.263 standard and the other an object-based video codec with flexible architecture based on ISO MPEG-4 standard currently under specification and planned to be finalized in 1998. These codes are an experimental implementations for examining the feasibility of real-time and/or flexible S/W-based video codecs operating in intra and/or internetworking environments.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1231-1234
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• 2007

This paper presents the overview of 3D video processing technologies for 3DTV such as 3D content generation, 3D video codec and video processing techniques for 3D displays. Some experimental results for 3D contents generation are shown in 3D mixed reality and 2D/3D conversion.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.168-171
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• 1988

This paper describes CODEC based on hybrid interframe and BTVQ including CRC(Conditional Replenishment Coding) system and RLC(Run Length Coding) method. Based upon the algorithm described in this paper, a practical CODEC has been designed for video conference and video phone use at 54Kbps using an ADSP-2100 as a CPU.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2020.07a
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• pp.510-512
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• 2020

In this paper, we reviewed the method on the codec-agnostic design of MPEG V-PCC. The codec-agnostic approach designed V-PCC can use any video codec for compression. Thus, adoption with other codecs beside HEVC has not been systematically discussed. Through the analysis of the design issues that related to MPEG EVC and JPEG. We provided a strategy on choosing and targeting different video codecs for V-PCC.