• Title/Summary/Keyword: variable-length code(VLC)

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A reversible variable length code with an efficient table memory (효율적인 테이블 메모리를 갖는 가역 가변길이 부호)

  • 임선웅;배황식;정정화
    • Proceedings of the IEEK Conference
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    • 2000.06c
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    • pp.133-136
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    • 2000
  • A RVLC(Reversible Variable Length Code) with an efficient table memory is proposed in this paper. In the conventional decoding methods, the weight of symbols and code values are used for the decoding table. These methods can be applied for Huffman decoding. In VLC decoding, many studies have been done for memory efficiency and decoding speed. We propose an improved table construction method for general VLC and RVLC decoding, which uses the transition number of bits within a symbol with an enhanced weight decomposition. In this method, tile table for RVLC decoding can be implemented with a smaller memory

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Iterative Symbol Decoding of Variable-Length Codes with Convolutional Codes

  • Wu, Hung-Tsai;Wu, Chun-Feng;Chang, Wen-Whei
    • Journal of Communications and Networks
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    • v.18 no.1
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    • pp.40-49
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    • 2016
  • In this paper, we present a symbol-level iterative source-channel decoding (ISCD) algorithm for reliable transmission of variable-length codes (VLCs). Firstly, an improved source a posteriori probability (APP) decoding approach is proposed for packetized variable-length encoded Markov sources. Also proposed is a recursive implementation based on a three-dimensional joint trellis for symbol decoding of binary convolutional codes. APP channel decoding on this joint trellis is realized by modification of the Bahl-Cocke-Jelinek-Raviv algorithm and adaptation to the non-stationary VLC trellis. Simulation results indicate that the proposed ISCD scheme allows to exchange between its constituent decoders the symbol-level extrinsic information and achieves high robustness against channel noises.

VLSI design of efficient VLC/VLD utilizing the characteristics of MPEG DCT coefficients (MPEG DCT 계수의 특징을 이용한 효율적인 VLC/VLD의 VLSI 설계)

  • Kong, Jong-Pil;Kim, Young-Min
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.33B no.1
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    • pp.79-86
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    • 1996
  • In this paper we propose an architecture for VLC(Variable Length Coder) and VLD(Variable Length Decoder) which is simple with respect to implementation point and efficient in memory. We implemented encoding and decoding circuit where we need only 7-bit address memory space for 114 MPEG1 DCT coefficients and employed minimal number of flip-flops and logics for an architecture to integrate a shift register for serial-to-parallel or parallel-to-serial conversion of the data in code mapping ROM. We obtained 50Mbps operating speed in both encoding and decoding process as the result of simulation using 0.80.8${\mu}m$ CMOS standard cells.

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Design of CAVLC Decoder for H.264/AVC (H.264/AVC용 CAVLC 디코더의 설계)

  • Jung, Duck-Young;Sonh, Seung-Il
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.11 no.6
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    • pp.1104-1114
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    • 2007
  • Digital video compression technique has played an important role that enables efficient transmission and storage of multimedia data where bandwidth and storage space are limited. The new video coding standard, H.264/AVC, developed by Joint Video Team(JVT) significantly outperforms previous standards in compression performance. Especially, variable length code(VLC) plays a crucial pun in video and image compression applications. H.264/AVC standard adopted Context-based Adaptive Variable Length Coding(CAVLC) as the entropy coding method. CAVLC of H.264/AVC requires a large number of the memory accesses. This is a serious problem for applications such as DMB and video phone service because of the considerable amount of power that is consumed in accessing the memory. In order to overcome this problem in this paper, we propose a variable length technique that implements memory-free coeff_token, level, and run_before decoding based on arithmetic operations and using only 70% of the required memory at total_zero variable length decoding.

Resynchronization of Modified JPEG Using a Power Allocation Scheme in a Direct Sequence CDMA System

  • Yim, Choon-Sik;Roh, Jae-Sung;Choi, Eun-Suk;Baek, Joong-Hwan;Cho, Sung-Joon
    • ETRI Journal
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    • v.24 no.5
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    • pp.405-408
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    • 2002
  • In this paper, we discuss recovery schemes for errors occurring when image data encoded with variable length coding (VLC) is transmitted through additive white Gaussian noise (AWGN) and multiple-access interference in direct sequence code division multiple access (DS/CDMA) systems. VLC such as JPEG is so sensitive to channel errors that severe degradation in decoded images occurs even if only one or two bits have errors. This is due to the loss of synchronization at the image decoder. We propose a resynchronization scheme using a power allocation method in wireless DS/CDMA transmission. Through simulation, we know that the proposed method has a more robust resynchronization capability and higher objective and subjective quality than the conventional method.

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Design of CAVLC Encoder for the Compressed Image in H.264/AVC (H.264/AVC에 적용 가능한 압축영상용 CAVLC 인코더 설계)

  • Jung, Duck-Young;Choi, Dug-Young;Sonh, Seung-Il
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • v.9 no.2
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    • pp.299-302
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    • 2005
  • 요즘 시대는 영상 기술과 IT 발전으로 다양한 멀티미디어 서비스를 제공하기 위해 고품질의 비디오와 높은 데이터 압축을 요구하게 되었고, 이를 위해 MPEG-4 AVC/H.264에서는 기존의 MPEG-4에서 채택한 VLC 기술과 유사한 Context-based Adaptive Variable Length Code(CAVLC)기술을 채택하여 이를 가능하게 하였다. 특히 CAVLC 기술은 HDTV처럼 큰 영상 뿐 아니라 카메라폰이나 DMB등과 같은 영상에서 고품질의 영상을 보다 효율적으로 제공 한다. 본 논문은 최근의 이미지와 비디오 압축에 대한 요구에 따라 H.264/AVC와 MPEG4-PART 1-에서 표준으로 채택한 CAVLC의 부호화 과정을 연구하여 Visual C++언어를 이용한 최적화된 시뮬레이션과 CAVLC의 성능평가를 통한 최적화를 실시하였고, 최적화된 예측 정보를 바탕으로 CAVLC를 VHDL언어를 이용하여 하드웨어로 구현하였다.

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An Improvement of Still Image Quality Based on Error Resilient Entropy Coding for Random Error over Wireless Communications (무선 통신상 임의 에러에 대한 에러내성 엔트로피 부호화에 기반한 정지영상의 화질 개선)

  • Kim Jeong-Sig;Lee Keun-Young
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.43 no.3 s.309
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    • pp.9-16
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    • 2006
  • Many image and video compression algorithms work by splitting the image into blocks and producing variable-length code bits for each block data. If variable-length code data are transmitted consecutively over error-prone channel without any error protection technique, the receiving decoder cannot decode the stream properly. So the standard image and video compression algorithms insert some redundant information into the stream to provide some protection against channel errors. One of redundancies is resynchronization marker, which enables the decoder to restart the decoding process from a known state in the event of transmission errors, but its usage should be restricted not to consume bandwidth too much. The Error Resilient Entropy Code(EREC) is well blown method which can regain synchronization without any redundant information. It can work with the overall prefix codes, which many image compression methods use. This paper proposes EREREC method to improve FEREC(Fast Error-Resilient Entropy Coding). It first calculates initial searching position according to bit lengths of consecutive blocks. Second, initial offset is decided using statistical distribution of long and short blocks, and initial offset can be adjusted to insure all offset sequence values can be used. The proposed EREREC algorithm can speed up the construction of FEREC slots, and can improve the compressed image quality in the event of transmission errors. The simulation result shows that the quality of transmitted image is enhanced about $0.3{\sim}3.5dB$ compared with the existing FEREC when random channel error happens.

Design of Hardwired Variable Length Decoder for H.264/AVC (하드웨어 구조의 H.264/AVC 가변길이 복호기 설계)

  • Yu, Yong-Hoon;Lee, Chan-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.11
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    • pp.71-76
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    • 2008
  • H.264(or MPEG-4/AVC pt.10) is a high performance video coding standard, and is widely used. Variable length code (VLC) of the H.264 standard compresses data using the statistical distribution of values. A decoder parses the compressed bit stream and searches decoded values in lookup tables, and the decoding process is not easy to implement by hardware. We propose an architecture of variable length decoder(VLD) for the H.264 baseline profile(BP) L4. The CAVLD decodes syntax elements using the combination of arithmetic units and lookup tables for the optimized hardware architecture. A barral shifter and a first 1's detector parse NAL bit stream, and are shared by Exp-Golomb decoder and CAVLD. A FIFO memory between CAVLD and the reorder unit and a buffer at the output of the reorder unit eliminate the bottleneck of data stream. The proposed VLD is designed using Verilog-HDL and is implemented using an FPGA. The synthesis result using a 0.18um standard CMOS technology shows that the gate count is 22,604 and the decoder can process HD($1920{\times}1080$) video at 120MHz.

On the Adaptive 3-dimensional Transform Coding Technique Employing the Variable Length Coding Scheme (가변 길이 부호화를 이용한 적응 3차원 변환 부호화 기법)

  • 김종원;이신호;이상욱
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.30B no.7
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    • pp.70-82
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    • 1993
  • In this paper, employing the 3-dimensional discrete cosine transform (DCT) for the utilization of the temporal correlation, an adaptive motion sequence coding technique is proposed. The energy distribution in a 3-D DCT block, due to the nonstationary nature of the image data, varies along the veritical, horizontal and temporal directions. Thus, aiming an adaptive system to local variations, adaptive procedures, such as the 3-D classification, the classified linear scanning technique and the VLC table selection scheme, have been implemented in our approach. Also, a hybrid structure which adaptively combines inter-frame coding is presented, and it is found that the adaptive hybrid frame coding technique shows a significant performance gain for a moving sequence which contains a relatively small moving area. Through an intensive computer simulation, it is demonstrated that, the performance of the proposed 3-D transform coding technique shows a close relation with the temporal variation of the sequence to be code. And the proposed technique has the advantages of skipping the computationally complex motion compensation procedure and improving the performance over the 2-D motion compensated transform coding technique for rates in the range of 0.5 ~ 1.0 bpp.

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