• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.983-986
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• 2003

This paper describes a 2.5V 80dB 360MHz CMOS VGA. A new variable degeneration resistor is proposed where the dc voltage drop over the degeneration resistor is minimized and employed in designing a low-voltage and high-speed CMOS VGA. HSPICE simulation results using a 0.25${\mu}{\textrm}{m}$ CMOS process parameters show that the designed VGA provides a 3dB bandwidth of 360MHz and a 80dB gain control range in 2dB step. Gain errors are less than 0.4dB at 200MHz and less than 1.4dB at 300MHz. The designed circuit consumes 10.8mA from a 2.5V supply and its die area is 1190${\mu}{\textrm}{m}$$\times$360${\mu}{\textrm}{m}$.

• ETRI Journal
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• v.28 no.3
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• pp.386-388
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• 2006

Monolithic SiGe heterojunction bipolar transistor (HBT) variable gain amplifiers (VGAs) with a feedforward configuration have been newly developed for 5 GHz applications. Two types of the feedforward VGAs have been made: one using a coupled-emitter resistor and the other using an HBT-based current source. At 5.2 GHz, both of the VGAs achieve a dynamic gain-control range of 23 dB with a control-voltage range from 0.4 to 2.6 V. The gain-tuning sensitivity is 90 mV/dB. At $V_{CTRL}$= 2.4 V, the 1 dB compression output power, $P_{1-dB}$, and dc bias current are 0 dBm and 59 mA in a VGA with an emitter resistor and -1.8 dBm and 71mA in a VGA with a constant current source, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.5A
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• pp.497-502
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• 2007

Broadband monolithic SiGe HBT variable gain amplifier with a feedforward configuration have been newly developed to improve bandwidth and dB-linearly controlled gain characteristics. The VGA has been implemented in a $0.35-{\mu}m$ BiCMOS process. The VGA achieves a dynamic gain-control range of 19.6 dB and a 3-dB bandwidth of 4 GHz ($4{\sim}8\;GHz$) with the control-voltage range from 0.6 to 2.6 V. The VGA produces a maximum gain of 9.3 dB at 6 GHz and a output power of -3 dBm at 8 GHz.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.8 no.3
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• pp.83-90
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• 2009

This paper presents the design and measurement of a flight model for a Ku-Band Linearized Channel Amplifier. All MMICs, Variable Gain Amplifier (VGA), Variable Voltage Attenuator ('.IVA), Branch line Coupler and Detector for Pre-distorter are fabricated using a Thin-Film Hybrid process. The performance of the fabricated module is verified through the radio frequency circuit simulation tool and electrical function test in space environment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.318-330
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• 2013

This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in $0.18-{\mu}m$ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from -11 dB to 10 dB with a gain error of less than ${\pm}0.33$ dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270MHz at the maximum gain, respectively. The PGA occupies a chip area of $0.04mm^2$ and consumes only 1.3 mA from the 1.8 V supply.

• 한국ITS학회:학술대회논문집
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• 2008.11a
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• pp.185-188
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• 2008

• Journal of Satellite, Information and Communications
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• v.3 no.1
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• pp.1-7
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• 2008

This Paper studied the design and measured results of a flight model for Ku-Band Linearized Channel Amplifier (LCAMP) for communication satellite onboard system. All MMICs, i.e. Variable Gain Amplifier (VGA), Variable Voltage Attenuator (VVA) with analog/digital attenuator, Branch line Hybrid Coupler and Detector for Pre-distorter are fabricated using Thin-Film Hybrid process. The performance of the fabricated module is verified through Radio Frequency circuit simulations and electrical function test in space environment for flight model at 12.25 to 12.75 GHz.

• Journal of IKEEE
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• v.22 no.2
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• pp.408-412
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• 2018

In this paper, a 26GHz variable gain amplifier fabricated using a 40nm CMOS process is studied. In the case of an automobile radar using 79 GHz, it is advantageous in designing and driving to drive down to a low frequency band or to use a low frequency band before up conversion rather than designing and matching the entire circuit to 79 GHz in terms of frequency characteristics. In the case of a Phased Array System that uses time delay through TTD (True Time Delay) in practice, down conversion to a lower frequency is advantageous in realizing a real time delay and reducing errors. For a VGA (Variable Gain Amplifier) operating in the 26GHz frequency band that is 1/3 of the frequency of 79GHz, VDD : 1V, Bias 0.95V, S11 is designed to be <-9.8dB (Mea. High gain mode) and S22 < (Mea. high gain mode), Gain: 2.69dB (Mea. high gain mode), and P1dB: -15 dBm (Mea. high gain mode). In low gain mode, S11 is <-3.3dB (Mea. Low gain mode), S22 <-8.6dB (Mea. low gain mode), Gain: 0dB (Mea. low gain mode), P1dB: -21dBm (Mea. Low gain mode).

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.22-28
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• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.4
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• pp.282-291
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• 2010

This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ${\mu}m$ CMOS technology and the die area is 5 mm $\times$ 5 mm. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 dB and 41 dB, respectively. The power consumption of the transmitter and receiver are 160 mW and 250 mW from the supply voltage of 2.5 V, respectively.