• Applied Chemistry for Engineering
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• v.20 no.6
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• pp.617-621
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• 2009

Zinc oxide (ZnO) nanorods were grown on the pre-oxidized silicon substrate with the assistance of Au and the fluorine-doped tin oxide (FTO) based on the catalysts by vapor-liquid-solid (VLS) synthesis. Two types of ZnO powder particle size, 20nm, $20{\mu}m$, were used as a source material, respectively The properties of the nanorods such as morphological characteristics, chemical composition and crystalline properties were examined by X-ray diffraction (XRD), energy-dispersive X-ray spectroscopy (EDX) and field-emission scanning electron microscope (FE-SEM). The particle size of ZnO source strongly affected the growth of ZnO nanostructures as well as the crystallographic structure. All the ZnO nanostructures are hexagonal and single crystal in nature. It is found that $1030^{\circ}C$ is a suitable optimum growth temperature and 20 nm is a optimum ZnO powder particle size. Nanorods were fabricated on the FTO deposition with large electronegativity and we found that the electric potential of nanorods rises as the ratio of current rises, there is direct relationship with the catalysts, Therefore, it was considered that Sn can be the alternative material of Au in the formation of ZnO nanostructures.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.289-289
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• 2013

While there are plenty of studies on synthesizing semiconducting germanium nanowires (Ge NWs) by vapor-liquid-solid (VLS) process, it is difficult to inject dopants into them with uniform dopants distribution due to vapor-solid (VS) deposition. In particular, as precursors and dopants such as germane ($GeH_4$), phosphine ($PH_3$) or diborane ($B_2H_6$) incorporate through sidewall of nanowire, it is hard to obtain the structural and electrical uniformity of Ge NWs. Moreover, the drastic tapered structure of Ge NWs is observed when it is synthesized at high temperature over $400^{\circ}C$ because of excessive VS deposition. In 2006, Emanuel Tutuc et al. demonstrated Ge NW pn junction using p-type shell as depleted layer. However, it could not be prevented from undesirable VS deposition and it still kept the tapered structures of Ge NWs as a result. Herein, we adopt $C_2H_2$ gas in order to passivate Ge NWs with carbon sheath, which makes the entire Ge NWs uniform at even higher temperature over $450^{\circ}C$. We can also synthesize non-tapered and uniformly doped Ge NWs, restricting incorporation of excess germanium on the surface. The Ge NWs with carbon sheath are grown via VLS process on a $Si/SiO_2$ substrate coated 2 nm Au film. Thin Au film is thermally evaporated on a $Si/SiO_2$ substrate. The NW is grown flowing $GeH_4$, HCl, $C_2H_2$ and PH3 for n-type, $B_2H_6$ for p-type at a total pressure of 15 Torr and temperatures of $480{\sim}500^{\circ}C$. Scanning electron microscopy (SEM) reveals clear surface of the Ge NWs synthesized at $500^{\circ}C$. Raman spectroscopy peaked at about ~300 $cm^{-1}$ indicates it is comprised of single crystalline germanium in the core of Ge NWs and it is proved to be covered by thin amorphous carbon by two peaks of 1330 $cm^{-1}$ (D-band) and 1590 $cm^{-1}$ (G-band). Furthermore, the electrical performances of Ge NWs doped with boron and phosphorus are measured by field effect transistor (FET) and they shows typical curves of p-type and n-type FET. It is expected to have general potentials for development of logic devices and solar cells using p-type and n-type Ge NWs with carbon sheath.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.346-346
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• 2011

실리콘 나노와이어는 높은 표면적으로 인해 뛰어난 감지 능력을 가지는 재료 중 하나로 다양한 센서 응용 분야에 사용되고 있다. 이를 제작하는 방법에는 Micro Electro Mechanical Systems (MEMS) 공정을 이용한 Top-down 방식과 Vapor-Liquid-Solid (VLS) 공정을 이용한 Bottom-up 방식이 널리 사용되고 있다. 특히 Plasma-Enhanced Chemical Vapor Deposition(PECVD)와 Au 촉매를 이용한 Bottom-up 방식은 수십 나노미터 이하의 실리콘 나노와이어를 간단한 변수 조절을 통해 성장시킬 수 있다. 또한 Au/Si의 공융점인 363$^{\circ}C$보다 낮은 온도에서 $SiH_4$를 분해시킬 수 있어 열적 효과로 인한 손실을 줄일 수 있는 장점을 지니고 있다. 하지만 PECVD를 이용한 실리콘 나노와이어 성장은 VLS 공정을 통해 표면으로부터 수직으로 성장하게 되는데 이는 센서 응용을 위한 전극 사이의 수평 연결 어려움을 지니고 있다. 따라서 이를 피하기 위한 표면 성장된 실리콘 나노와이어가 요구된다. 본 연구에서는 PECVD VLS 공정을 이용하여 $HAuCl_4$를 촉매로 이용한 표면 성장된 Tree-like 실리콘 나노와이어를 성장시켰다. 공정가스로는 $SiH_4$와 이를 분해시키기 위해 Ar 플라즈마를 사용 하였고 웨이퍼 표면에 HAuCl4를 분사하고 고진공 상태에서 챔버 기판을 370$^{\circ}C$까지 가열한 후 플라즈마 파워(W) 및 공정 압력(mTorr)을 변수로 두어 실험을 진행하였다. 기존의 보고된 연구와 달리 환원된 금 입자 대신 $HAuCl_4$용액을 그대로 사용하였는데 이는 표면 조도(Surface roughness)를 가지는 Au 박막 상태로 존재하게 된다. 이 중 마루(Asperite) 부분에 PECVD로부터 발생된 실리콘 나노 입자가 상대적으로 높은 확률로 흡착하게 되어 실리콘 나노와이어의 표면성장을 유도하게 된다. 성장된 실리콘 나노와이어는 SEM과 EDS를 이용하여 직경, 길이 및 화학적 성분을 측정하였다. 직경은 약 100 nm, 길이는 약 10 ${\mu}m$ 정도로 나타났으며 Tree-like 실리콘 나노와이어가 성장되었다. 향후 전극이 형성된 기판위에 이를 직접 성장시킴으로써 이 물질의 I-V 특성을 파악 할 것이며 이는 센서 응용 분야에 도움이 될 것으로 기대된다.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.11a
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• pp.150-150
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• 2003

wide bind gap과 wurtzite hexagonal structure를 가지고 있으며 청색 발광 및 청자색 레이저 특성을 보이는 III-V족 화합물반도체 GaN는 laser diodes (LD) 및 light emitting diodes (LED) 재료로 주목받고있는 주요 전자재료이다. 본 연구에서는 GaN를 chemical vapor deposition (CVD) 법을 이용하여 vapor-liquid-solid (VLS) mechanisum에 의하여 GaN나노와이어 형태로 성장시켰다. 기판은 (001)Si을 사용하였고 suputtering을 이용하여 GaN와 AlN의 double buffer layer (DBL)를 증착시켰으며 촉매로는 Ni을 사용하였다. 또한, 원료로는 고순도 Ga금속과 NH$_3$ gas를, carrier gas로는 Ar을 사용하여 GaN/AlN/(001)Si 위에 GaN 나노와이어를 성장시켰다. 성장된 GaN 나노와이어는 DBL의 두께, Ga source의 양, 튜브 안의 압력, 튜브 안의 위치 등의 제 공정변수에 따라 tangled, straight 등의 다양한 형상을 보였으며 지름은 약 30~100 nm, 길이는 수 $\mu\textrm{m}$로 관찰되었다. GaN나노와이어의 결정성, 형상 및 발광특성 등을 x-ray diffraction (XRD), photoluminesence (PL), scanning electron microscope (SEM), transmision electron microscope (TEM) 등을 이용하여 측정하였으며 제 공정변수와의 상관관계를 규명하였다.

• Bulletin of the Korean Chemical Society
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• v.30 no.7
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• pp.1563-1566
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• 2009

One-dimensional aluminum nitride (AlN) nanostructures were synthesized by calcining an Al(OH)(succinate) complex, which contained a very small amount of iron as a catalyst, under a mixed gas flow of nitrogen and CO (1 vol%). The complex decomposed into a homogeneous mixture of alumina and carbon at the molecular level, resulting in the lowering of the formation temperature of the AlN nanostructures. The morphology of the nanostructures such as nanocone, nanoneedle, nanowire, and nanobamboo was controlled by varying the reaction conditions, including the reaction atmosphere, reaction temperature, duration time, and ramping rate. Iron droplets were observed on the tips of the AlN nanostructures, strongly supporting that the nanostructures grow through the vapor-liquid-solid mechanism. The variation in the morphology of the nanostructures was well explained in terms of the relationship between the diffusion rate of AlN vapor into the iron droplets and the growth rate of the nanostructures.

• Journal of Powder Materials
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• v.13 no.5 s.58
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• pp.305-312
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• 2006

Amorphous carbon nanotubes were synthesized by a reaction of benzene, ferrocene and Na mixture in a small autoclave at temperatures as low as $400^{\circ}C$. The resulting carbon nanotubes were short and straight, but their inner hole was filled with residual products. The addition of quartz to the reacting mixture considerably promoted the formation of carbon nanotubes. A careful examination of powder structure suggested that the nanotubes in this process were mainly formed by surface diffusion of carbon atoms at the surface of solid catalytic particles, not by VLS(vapor-liquid-solid) mechanism.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.17 no.3
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• pp.91-94
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• 2007

Single-crystalline $SnO_2$ nanowires were successfully grown on Si(001) substrates via vapor-liquid-solid mechanism in a thermal chemical vapor deposition. Large quantity of $SnO_2$ nanowires were synthesized at temperature ranges of $950{\sim}1000^{\circ}C$ in Ar atmosphere. It was found that the grown $SnO_2$ nanowires are of a tetragonal rutile structure and single crystalline by diffraction and transmission electron microscopy measurements. Broad emission located at about 600 m from the grown nanowires was clearly observed in room temperature photoluminescence measurements, indicating that the emission band originated from defect level transition into $SnO_2$ nanowires.

• Transactions on Electrical and Electronic Materials
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• v.14 no.3
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• pp.148-151
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• 2013

The control of Ga doping in ZnO nanowires (NWs) by physical vapor deposition has been implemented and characterized. Various Ga-doped ZnO NWs were grown using the vapor-liquid-solid (VLS) method, with Au catalyst on c-plane sapphire substrate by hot-walled pulsed laser deposition (HW-PLD), one of the physical vapor deposition methods. The structural, optical and electrical properties of Ga-doped ZnO NWs have been systematically analyzed, by changing Ga concentration in ZnO NWs. We observed stacking faults and different crystalline directions caused by increasing Ga concentration in ZnO NWs, using SEM and HR-TEM. A $D^0X$ peak in the PL spectra of Ga doped ZnO NWs that is sharper than that of pure ZnO NWs has been clearly observed, which indicated the substitution of Ga for Zn. The electrical properties of controlled Ga-doped ZnO NWs have been measured, and show that the conductance of ZnO NWs increased up to 3 wt% Ga doping. However, the conductance of 5 wt% Ga doped ZnO NWs decreased, because the mean free path was decreased, according to the increase of carrier concentration. This control of the structural, optical and electrical properties of ZnO NWs by doping, could provide the possibility of the fabrication of various nanowire based electronic devices, such as nano-FETs, nano-inverters, nano-logic circuits and customized nano-sensors.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.36.1-36.1
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• 2011

1차원 양자 구속 효과로 인해 우수한 전하 전송 특성을 갖는 나노선을 차세대 전자소자에 응용하기 위한 일환으로, 실리콘 기판 상에 동일한 실리콘 나노선을 성장하고 이의 미세구조 특징을 분석하였다. 실리콘 나노선은 Au 시드층을 형성한 후 화학기상증착법을 이용한 VLS (vapor-liquid-solid) 공법으로 성장시켰으며, 시드층의 크기에 따른 나노선의 구조 특성을 이미지 프로세싱을 통해 통계분석하였다. 성장된 실리콘 나노선의 결정구조와 성분을 고해상도 투과전자현미경과 EDAX를 이용하여 분석하였으며, 성장 온도 조건에 따른 나노선의 morphology 특성도 실시하였다. 그 결과 Au 시드층의 성분이 나노선과 기판의 계면에서 상당 부분 잔류함과, 성장된 나노선에는 쌍정 결함(twin defect) 등의 결정구조 변화가 수반됨을 알 수 있었다. 또한 금속 시드층의 평균 입도와 성장 온도 및 소스 가스 유량 조절함으로써 실리콘 나노선의 직경과 길이를 최적화 할 수 있었다. 이를 통해 향후 공정 스케일 다운의 한계 상황에 도달하고 있는 반도체 트랜지스터 소자를 대체할 수 있는 나노선 반도체 소자에 대한 공정기술 개발과 이를 이용한 다양한 응용 분야도 동시에 제시할 수 있게 되었다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.23-23
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• 2009

Recently, the nanowire configuration of GST showed nanosecond-level phase switch at very low power dissipation, suggesting that the nanowires could be ideal for data storage devices. In spite of many advantages of IST materials, their feasibility in both thin films and nanowires for electronic memories has not been extensively investigated. The synthesis of the chalcogenide nanowires was mainly preformed via a vapor transport process such as vapor-liquid-solid (VLS) growth at a high temperature. However, in this study, IST nanowires as well as thin films were prepared at a low temperature (${\sim}250^{\circ}C$) by metal organic chemical vapor deposition(MOCVD) method, which is possible for large area deposition. The IST films and/or nanowires were selectively grown by a control of working pressure at a constant growth temperature by MOCVD. In-Sb-Te NWs will be good candidate materials for high density PRAM applications. And MOCVD system is powerful for applying ultra scale integration cell.