• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.139-139
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• 2010

금속 실리사이드 나노입자는 열적 및 화학적 안정성이 뛰어나고, 절연막내에 일함수 차이에 따라 깊은 양자 우물구조가 형성되어 비휘발성 메모리 소자를 제작할 수 있다. 그러나 단일 $SiO_2$ 절연막을 사용하였을 경우 저장된 전하의 정보 저장능력 및 쓰기/지우기 시간을 향상시키는 데 물리적 두께에 따른 제한이 따른다. 본 연구에서는 터널장벽 엔지니어링을 통하여 물리적인 두께는 단일 $SiO_2$ 보다는 두꺼우나 쓰기/지우기 동작을 위하여 인가되는 전기장에 의하여 상대적으로 전자가 느끼는 상대적인 터널 절연막 두께를 감소시키는 방법으로 동작속도를 향상 시킨 $SiO_2/Si_3N_4/SiO_2$ 및 $Si_3N_4/SiO_2/Si_3N_4$ 터널 절연막을 사용한 금속 실리사이드 나노입자 비휘발성 메모리를 제조하였다. 제조방법은 우선 p-type 실리콘 웨이퍼 위에 100 nm 두께로 증착된 Poly-Si 층을 형성 한 이후 소스와 드레인 영역을 리소그래피 방법으로 형성시켜 트랜지스터의 채널을 형성한 이후 그 상부에 $SiO_2/Si_3N_4/SiO_2$ (2 nm/ 2 nm/ 3 nm) 및 $Si_3N_4/SiO_2/Si_3N_4$ (2 nm/ 3 nm/ 3 nm)를 화학적 증기 증착(chemical vapor deposition)방법으로 형성 시킨 이후, direct current magnetron sputtering 방법을 이용하여 2~5 nm 두께의 $WSi_2$ 및 $TiSi_2$ 박막을 증착하였으며, 나노입자 형성을 위하여 rapid thermal annealing(RTA) system을 이용하여 $800{\sim}1000^{\circ}C$에서 질소($N_2$) 분위기로 1~5분 동안 열처리를 하였다. 이후 radio frequency magnetron sputtering을 이용하여 $SiO_2$ control oxide layer를 30 nm로 증착한 후, RTA system을 이용하여 $900^{\circ}C$에서 30초 동안 $N_2$ 분위기에서 후 열처리를 하였다. 마지막으로 thermal evaporator system을 이용하여 Al 전극을 200 nm 증착한 이후 리소그래피와 식각 공정을 통하여 채널 폭/길이 $2{\sim}5{\mu}m$인 비휘발성 메모리 소자를 제작하였다. 제작된 비휘발성 메모리 소자는 HP 4156A semiconductor parameter analyzer와 Agilent 81101A pulse generator를 이용하여 전기적 특성을 확인 하였으며, 측정 온도를 $25^{\circ}C$, $85^{\circ}C$, $125^{\circ}C$로 변화시켜가며 제작된 비휘발성 메모리 소자의 열적 안정성에 관하여 연구하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.130.2-130.2
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• 2013

Today, chemical vapor deposition (CVD) of hydrocarbon gases has been demonstrated as an attractive method to synthesize large-area graphene layers. However, special care should be taken to precisely control the resulting graphene layers in CVD due to its sensitivity to various process parameters. Therefore, a facile synthesis to grow graphene layers with high controllability will have great advantages for scalable practical applications. In order to simplify and create efficiency in graphene synthesis, the graphene growth by thermal annealing process has been discussed by several groups. However, the study on growth mechanism and the detailed structural and optoelectronic properties in the resulting graphene films have not been reported yet, which will be of particular interest to explore for the practical application of graphene. In this study, we report the growth of few-layer, large-area graphene films using rapid thermal annealing (RTA) without the use of intentional carbon-containing precursor. The instability of nickel films in air facilitates the spontaneous formation of ultrathin (<2~3 nm) carbon- and oxygen-containing compounds on a nickel surface and high-temperature annealing of the nickel samples results in the formation of few-layer graphene films with high crystallinity. From annealing temperature and ambient studies during RTA, it was found that the evaporation of oxygen atoms from the surface is the dominant factor affecting the formation of graphene films. The thickness of the graphene layers is strongly dependent on the RTA temperature and time and the resulting films have a limited thickness less than 2 nm even for an extended RTA time. The transferred films have a low sheet resistance of ~380 ${\Omega}/sq$, with ~93% optical transparency. This simple and potentially inexpensive method of synthesizing novel 2-dimensional carbon films offers a wide choice of graphene films for various potential applications.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.250-250
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• 2013

단일벽 탄소나노튜브(Single-walled nanotubes, SWNTs)는 나노스케일의 크기와 우수한 물성으로 인하여, 전자, 에너지, 바이오 분야로의 응용이 기대되고 있다. 특히 SWNTs의 직경을 제어하게 되면 튜브의 전도성 제어가 훨씬 수월하게 되어, 차세대 나노전자소자의 실현을 앞당길 수 있으며 이러한 이유로 많은 연구들이 현재 행해지고 있다. SWNTs의 직경제어 합성을 위해서는 현재 열화학기상증착법(Thermal chemical vapor deposition; TCVD)이 가장 일반적으로 이용되고 있으며, 합성 촉매와 합성되는 튜브의 직경과의 크기 연관성이 알려진 후로는, 촉매의 크기를 제어하여 SWNTs의 직경을 제어하고자 하는 연구들이 활발하게 보고되고 있다. 특히, 촉매 나노입자의 직경이 1~2 nm 이하로 감소될 경우, SWNTs의 직경 분포가 어떻게 변화할 것인지가 최근 가장 중요한 관심사로 남아 있으나, 이러한 크기의 금속입자는 나노입자의 융점저하 현상이 발현되는 영역이므로, SWNTs의 합성온도 영역에서 촉매 금속입자는 반액체(Semi-liquid) 상태로 존재할 것으로 추측하고 있다. 본 연구에서는 고온의 SWNTs 합성환경에서 금속나노촉매의 유동성을 제한하기 위하여 나노사이즈의 기공이 규칙적으로 정렬된 다공성 물질인 제올라이트를 촉매담지체로 이용하였고, 이 때 다양한 합성변수가 SWNTs의 직경에 미치는 영향을 살펴보고자 하였다. SWNTs의 합성을 위해 실리콘 산화막 기판 위에 제올라이트를 도포한 후, 합성 촉매로서 전자빔증발법을 통하여 수 ${\AA}$에서 수 nm 두께의 철 박막을 증착하였다. 합성은 메탄을 원료가스로 하여 TCVD법으로 실시하였다. 주요변수로는 제올라이트 종류, 증착하는 철 박막의 두께, 합성온도를 설정하였으며, 이에 따라 합성된 SWNTs의 합성수율 및 직경분포의 변화를 체계적으로 살펴보았다. SWNTs의 전체적인 합성수율의 변화는 SEM 관찰결과를 이용하였으며, SWNTs의 직경은 AFM 관찰 및 Raman 스펙트럼의 분석에서 도출하였다. 실험결과, 제올라이트 종류에 따라서는 명확한 튜브직경 분포의 변화 없이 비교적 좁은 직경분포를 갖는 SWNTs가 합성되었으며, 합성온도가 $850^{\circ}C$ 이하로 감소되면 합성수율이 현저히 감소되는 것을 알 수 있었다. 촉매박막의 두께가 1 nm 이상인 경우에서는 직경 5 nm 전후의 나노입자가 형성되었으며, 이때 SWNTs의 합성수율은 높았으나 다양한 직경의 튜브가 합성이 된 것을 확인할 수 있었다. 반면, 촉매입자의 크기가 2 nm 이하에서는 합성수율은 다소 저하되었으나, SWNTs의 직경분포의 폭이 상대적으로 훨씬 좁아지는 것을 알 수 있었다. 추후, 극미세 촉매와 저온합성 환경에서의 합성수율 향상을 위한 합성공정의 개량이 지속적으로 요구된다.

• Korean Journal of Materials Research
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• v.2 no.5
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• pp.353-359
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• 1992

Thermal oxidation and plasma enhanced chemical vapor deposition of tantalum oxide thin films on p-type (100) Si substrates were studied to examine the dielectric nature of T$a_2O_5$ as a Al/T$a_2O_5$/p-Si capacitor. Microstructure and dielectric properties of the capacitors were investigated by XRD, AES, high frequency C-V analyzer, I-V meter and TEM. XRD analysis showed that the structure of T$a_2O_5$ films were amorphous, but the films were crystallized to hexagonal $\delta$-T$a_2O_5$ by 65$0^{\circ}C$ thermal oxidation treatment. It was found that the stoichiometry of the films was more or less close to 2 : 5. Leakage current density and relative dielectric constant of thermal oxidation T$a_2O_5$ film at 60$0^{\circ}C$ was 5.0${ imes}10^{-6}$/A/c$m^2 and 31.5, respectively. In the case of PECVD T$a_2O_5$film deposited at 0.47W/c$m^2 they were 2.5${ imes}10^{-5}$/A/$ extrm{cm}^2$ and 24.0, respectively. The morphology of the films and interfaces were investigated by TEM.

• Korean Journal of Materials Research
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• v.7 no.3
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• pp.175-179
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• 1997

bliniaturization oi microwave circuit components is an important issue with the development in the mobile communication. Capacitors, inductors anti hybrid devices of these are building blocks of electric circuits, and the fabrication of these devices using thin film technology will influence on the miniaturization of electronic devices In this paper, we report the successful fabrication of the inductors, capacitors and LC hybrid devices using a ferroelectric and a ferromagnetic oxide thin iilm. Au, stable at high temperatures in oxidizing ambient, is patterned by lift-off process, and oxide thin films are deposited by ion beam sputtering and chemical vapor deposition. These devices are characterized by a network analyzer in 0.5-15GtIz range We got the inductance of 5nH, capacitance oi 10, 000 pF and resonant frequencies of $10^{6}-10^{9}Hz$.

• Nuclear Engineering and Technology
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• v.42 no.6
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• pp.662-669
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• 2010

To develop the manufacturing methods for the blanket first wall (FW) of the International Thermonuclear Experimental Reactor (ITER) and to verify the integrity of the joint, Be/Cu mockups were fabricated and tested at the KoHLT-1 (Korea Heat Load Test facility), a graphite heater facility located at the Korea Atomic Energy Research Institute (KAERI). Since Be and Cu joining is the focus of the present study, the fabricated mockups had a CuCrZr heat sink joined with three Be tiles as an armor material, unlike the original ITER blanket FW, which has a stainless steel structure and coolant tubes. Hot isostatic pressing (HIP) was carried out at $580^{\circ}C$ and 100 MPa for 2 hours as the method for Be/Cu joining. Three interlayers, namely, $1{\mu}mCr/10{\mu}mCu$, $1{\mu}mTi/0.5{\mu}mCr/10{\mu}mCu$, and $5{\mu}mTi/10{\mu}mCu$ were applied as a coating to the Be tiles by a physical vapor deposition (PVD) method. A shear test was performed with the specimens, which were fabricated by the same methods as those used to fabricate the mockups. The average values were 125 MPa to 180 MPa, and the samples with the $1{\mu}mCr/10{\mu}mCu$ interlayer showed the lowest value. No defect or delamination was found in the joints of the mockups by the developed ultrasonic test using a flat-type probe with a 10 MHz frequency and a 0.25 inch diameter. High heat flux (HHF) tests were performed at $1.0\;MW/m^2$ heat flux for each mockup using the given conditions, and the results were analyzed by ANSYS-CFX code. For the test criteria, an expected fatigue lifetime about 1,000 cycles was obtained by analysis with ANSYS-mechanical code. Mockups using the interlayers of $1{\mu}mTi/0.5{\mu}mCr/10{\mu}mCu$ and $5{\mu}mTi/10{\mu}mCu$ survived up to 1,100 cycles over the required number of cycles. However, one of the Be tiles in the other two mockups using the $1{\mu}mCr/10{\mu}mCu$ interlayer was detached during the screening test, and others were detached by discharge after 862 cycles. The integrity of the joints using the proposed interlayers was proven by the HHF test, but the other interlayer requires more study before it can be used for the joining of Be to Cu. Moreover, it was confirmed that the measured temperatures agreed well with the analysis temperatures, which were used to estimate the lifetime and that the developed facility showed its capability of the long time operation.

• Korean Chemical Engineering Research
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• v.57 no.5
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• pp.706-713
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• 2019

In this study, basic research was conducted to provide guidelines for selecting printers and materials suitable for each application case by analyzing 3D printing method and surface characteristics of materials suitable for microfluidic system. We have studied the surface characteristics according to the materials for the two typical printing methods: The most commonly used method of Fused Deposition Modeling (FDM) printing and the relatively high resolution method of Stereolithography (SLA) printing. The FDM prints exhibited hydrophilic properties before post - treatment, regardless of the material, but showed hydrophobic properties after post - treatment with acetone vapor. It was confirmed by the observation of surface roughness using SEM that the change of the contact angle was due to the removal of the surface structure by post-treatment. SLA prints exhibited hydrophilic properties compared to FDM prints, but they were experimentally confirmed to be capable of surface modification using hydrophobic coatings. It was confirmed that it is impossible to make a transparent specimen in the FDM method. However, sufficient transparency is secured in the case of the SLA method. It is also confirmed that the electroporation chip of the digital electroporation system based on the droplet contact charging phenomenon was fabricated by the SLA method and the direct application to the microfluidic system by demonstrating the electroporation successfully.

• Korean Journal of Metals and Materials
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• v.46 no.11
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• pp.762-769
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• 2008

Hydrogenated amorphous silicon(a-Si : H) layers, 120 nm and 50 nm in thickness, were deposited on 200 $nm-SiO_2$/single-Si substrates by inductively coupled plasma chemical vapor deposition(ICP-CVD). Subsequently, 30 nm-Ni layers were deposited by E-beam evaporation. Finally, 30 nm-Ni/120 nm a-Si : H/200 $nm-SiO_2$/single-Si and 30 nm-Ni/50 nm a-Si:H/200 $nm-SiO_2$/single-Si were prepared. The prepared samples were annealed by rapid thermal annealing(RTA) from $200^{\circ}C$ to $500^{\circ}C$ in $50^{\circ}C$ increments for 30 minute. A four-point tester, high resolution X-ray diffraction(HRXRD), field emission scanning electron microscopy (FE-SEM), transmission electron microscopy (TEM), and scanning probe microscopy(SPM) were used to examine the sheet resistance, phase transformation, in-plane microstructure, cross-sectional microstructure, and surface roughness, respectively. The nickel silicide on the 120 nm a-Si:H substrate showed high sheet resistance($470{\Omega}/{\Box}$) at T(temperature) < $450^{\circ}C$ and low sheet resistance ($70{\Omega}/{\Box}$) at T > $450^{\circ}C$. The high and low resistive regions contained ${\zeta}-Ni_2Si$ and NiSi, respectively. In case of microstructure showed mixed phase of nickel silicide and a-Si:H on the residual a-Si:H layer at T < $450^{\circ}C$ but no mixed phase and a residual a-Si:H layer at T > $450^{\circ}C$. The surface roughness matched the phase transformation according to the silicidation temperature. The nickel silicide on the 50 nm a-Si:H substrate had high sheet resistance(${\sim}1k{\Omega}/{\Box}$) at T < $400^{\circ}C$ and low sheet resistance ($100{\Omega}/{\Box}$) at T > $400^{\circ}C$. This was attributed to the formation of ${\delta}-Ni_2Si$ at T > $400^{\circ}C$ regardless of the siliciation temperature. An examination of the microstructure showed a region of nickel silicide at T < $400^{\circ}C$ that consisted of a mixed phase of nickel silicide and a-Si:H without a residual a-Si:H layer. The region at T > $400^{\circ}C$ showed crystalline nickel silicide without a mixed phase. The surface roughness remained constant regardless of the silicidation temperature. Our results suggest that a 50 nm a-Si:H nickel silicide layer is advantageous of the active layer of a thin film transistor(TFT) when applying a nano-thick layer with a constant sheet resistance, surface roughness, and ${\delta}-Ni_2Si$ temperatures > $400^{\circ}C$.

• Korean Journal of Metals and Materials
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• v.47 no.5
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• pp.322-329
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• 2009

60 nm- and 20 nm-thick hydrogenated amorphous silicon (a-Si:H) layers were deposited on 200 nm $SiO_2/Si$ substrates using ICP-CVD (inductively coupled plasma chemical vapor deposition). A 10 nm-Ni layer was then deposited by e-beam evaporation. Finally, 10 nm-Ni/60 nm a-Si:H/200 nm-$SiO_2/Si$ and 10 nm-Ni/20 nm a-Si:H/200 nm-$SiO_2/Si$ structures were prepared. The samples were annealed by rapid thermal annealing for 40 seconds at $200{\sim}500^{\circ}C$ to produce $NiSi_x$. The resulting changes in sheet resistance, microstructure, phase, chemical composition and surface roughness were examined. The nickel silicide on a 60 nm a-Si:H substrate showed a low sheet resistance at T (temperatures) >$450^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate showed a low sheet resistance at T > $300^{\circ}C$. HRXRD analysis revealed a phase transformation of the nickel silicide on a 60 nm a-Si:H substrate (${\delta}-Ni_2Si{\rightarrow}{\zeta}-Ni_2Si{\rightarrow}(NiSi+{\zeta}-Ni_2Si)$) at annealing temperatures of $300^{\circ}C{\rightarrow}400^{\circ}C{\rightarrow}500^{\circ}C$. The nickel silicide on the 20 nm a-Si:H substrate had a composition of ${\delta}-Ni_2Si$ with no secondary phases. Through FE-SEM and TEM analysis, the nickel silicide layer on the 60 nm a-Si:H substrate showed a 60 nm-thick silicide layer with a columnar shape, which contained both residual a-Si:H and $Ni_2Si$ layers, regardless of annealing temperatures. The nickel silicide on the 20 nm a-Si:H substrate had a uniform thickness of 40 nm with a columnar shape and no residual silicon. SPM analysis shows that the surface roughness was < 1.8 nm regardless of the a-Si:H-thickness. It was confirmed that the low temperature silicide process using a 20 nm a-Si:H substrate is more suitable for thin film transistor (TFT) active layer applications.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.3
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• pp.443-450
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• 2021

After selecting a PES substrate with excellent thermal stability and optical properties among plastic substrates, a SiO₂ thin film was deposited as a buffer layer to a thickness of 20nm by plasma-enhanced chemical vapor deposition to compensate for the high moisture absorption. Then, the ITZO thin film was deposited by a RF magnetron sputtering method to investigate electrical and optical properties according to RF power. The ITZO thin film deposited at 50W showed the best electrical properties such as a resistivity of 8.02×10^-4 Ω-cm and a sheet resistance of 50.13Ω/sq.. The average transmittance of the ITZO thin film in the visible light region(400-800nm) was relatively high as 80% or more when the RF power was 40 and 50W. Figure of Merits (Φ_TC and FOM) showed the largest values of 23.90×10^-4 Ω^-1 and 5883 Ω^-1cm^-1, respectively, in the ITZO thin film deposited at 50W.