• 제목/요약/키워드: user verification

검색결과 593건 처리시간 0.027초

HDL 모델 마이크로프로세서의 MS-DOS 호환성 검증 환경 구현 (The environment for Verifying MS-DOS compatibility of HDL modeled microprocessor)

  • 이문기;이정엽;김영완;서광수
    • 전자공학회논문지A
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    • 제32A권7호
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    • pp.115-122
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    • 1995
  • This paper presents the simulation environment that verifies whether a new microprocessor described with HDL is compatible with MS-DOS. The phrase 'compatible with MS-DOS' means that the microprocessor can execute MS-DOS without any modification of MS-DOS's binary code. The proposed verification environment consists of HDL simulator and user interface module. And the communications between them are performed by using sockets which UNIXprovide. The HDL simulator is equipped with several functions, which use PLI to emulate ROM-BIOS facilities. The ROM-BIOS emulation routine is described by using these functions. User interface module utilizes S/MOTIF and participates in emulating PC monitor and keyboard. The verification environment is tested by executing the MS-DOS commands (DIR, FORMAT, DATE, TIME etc.) with the HDL model of microprocessor, and the display of user interface module verifies that the environment works correctly. In this paper, the method of constructing the verification environment is presented, and the simulation results are summarized.

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음성인식과 지문식별에 기초한 가상 상호작용 (Virtual Interaction based on Speech Recognition and Fingerprint Verification)

  • 김성일;오세진;김동헌;이상용;황승국
    • 한국지능시스템학회:학술대회논문집
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    • 한국퍼지및지능시스템학회 2006년도 춘계학술대회 학술발표 논문집 제16권 제1호
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    • pp.192-195
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    • 2006
  • In this paper, we discuss the user-customized interaction for intelligent home environments. The interactive system is based upon the integrated techniques using speech recognition and fingerprint verification. For essential modules, the speech recognition and synthesis were basically used for a virtual interaction between the user and the proposed system. In experiments, particularly, the real-time speech recognizer based on the HM-Net(Hidden Markov Network) was incorporated into the integrated system. Besides, the fingerprint verification was adopted to customize home environments for a specific user. In evaluation, the results showed that the proposed system was easy to use for intelligent home environments, even though the performance of the speech recognizer was not better than the simulation results owing to the noisy environments

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고성능 동적 서명인증시스템 구현 (Implementation of Advanced Dynamic Signature Verification System)

  • 김진환;조혁규;차의영
    • 한국정보통신학회논문지
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    • 제9권4호
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    • pp.890-895
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    • 2005
  • 동적(온라인) 서명인증시스템은 내부 처리 과정에서는 불필요한 점들을 제거하는 전처리과정, 서명의 변화폭을 줄여주고 서명자의 고유한 특징 정보를 추출하는 특징추출과정, 두 서명의 특징벡터를 비교하여 유사도를 계산하는 비교과정, 보안수준에 따른 인증 여부를 결정하는 판단과정으로 구성되며, 사용자 관점에서의 화면 구성은 서명을 입력받아 기준서명과 보안수준 값을 만들어 주는 등록화면과 권한 부여를 위하여 진서명인지 모조서명인지를 판단하는 인증화면으로 나누어진다. 본 논문에서는 동적 서명인증시스템의 처리 속도, 서명의 특징벡터의 추출방법과 비교 알고리즘, 사용자 인터페이스 등과 실제 환경에서의 설계 및 구현에 대한 연구이다.

A Privacy-preserving Data Aggregation Scheme with Efficient Batch Verification in Smart Grid

  • Zhang, Yueyu;Chen, Jie;Zhou, Hua;Dang, Lanjun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • 제15권2호
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    • pp.617-636
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    • 2021
  • This paper presents a privacy-preserving data aggregation scheme deals with the multidimensional data. It is essential that the multidimensional data is rarely mentioned in all researches on smart grid. We use the Paillier Cryptosystem and blinding factor technique to encrypt the multidimensional data as a whole and take advantage of the homomorphic property of the Paillier Cryptosystem to achieve data aggregation. Signature and efficient batch verification have also been applied into our scheme for data integrity and quick verification. And the efficient batch verification only requires 2 pairing operations. Our scheme also supports fault tolerance which means that even some smart meters don't work, our scheme can still work well. In addition, we give two extensions of our scheme. One is that our scheme can be used to compute a fixed user's time-of-use electricity bill. The other is that our scheme is able to effectively and quickly deal with the dynamic user situation. In security analysis, we prove the detailed unforgeability and security of batch verification, and briefly introduce other security features. Performance analysis shows that our scheme has lower computational complexity and communication overhead than existing schemes.

손금과 손바닥 정맥을 함께 이용한 심층 신경망 기반 사용자 인식 (User Identification Method using Palm Creases and Veins based on Deep Learning)

  • 김슬빈;김원준
    • 방송공학회논문지
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    • 제23권3호
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    • pp.395-402
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    • 2018
  • 손바닥은 손금, 정맥 등 고유한 특징 정보를 포함하고 있는 신체 부위로 이를 이용한 다양한 사용자 인식 방법이 지속적으로 연구되어 왔다. 본 논문에서는 손금과 손바닥 정맥을 함께 이용한 사용자 인식 방법을 제안한다. 먼저, 손바닥 영역에서 손금과 정맥이 가장 많이 포함되어 있는 관심 영역을 검출하고, 에지 방향성 및 밝기 통계정보를 이용하여 정맥 영상 화질 개선을 수행한다. 이후 다중 스펙트럼 환경에서 획득된 복수의 영상을 각각 독립된 심층 신경망의 입력으로 이용하여 손금과 정맥 패턴을 효과적으로 학습한다. 다양한 상황에서의 실험을 통해 본 논문에서 제안하는 방법이 기존 사용자 인식 방법 대비 개선된 결과를 보임을 확인하고 그 결과를 분석한다.

가변 문턱치와 순차결정법을 통한 문맥요구형 화자확인 (Text-Prompt Speaker Verification using Variable Threshold and Sequential Decision)

  • 안성주;강선미;고한석
    • 음성과학
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    • 제7권4호
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    • pp.41-47
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    • 2000
  • This paper concerns an effective text-prompted speaker verification method to increase the performance of speaker verification. While various speaker verification methods have already been developed, their effectiveness has not yet been formally proven in terms of achieving an acceptable performance level. It is also noted that the traditional methods were focused primarily on single, prompted utterance for verification. This paper, instead, proposes sequential decision method using variable threshold focused at handling two utterances for text-prompted speaker verification. Experimental results show that the proposed speaker verification method outperforms that of the speaker verification scheme without using the sequential decision by a factor of up to 3 times. From these results, we show that the proposed method is highly effective and achieves a reliable performance suitable for practical applications.

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FX3 USB 3 브릿지 칩과 slave FIFO 인터페이스를 사용하는 FPGA 검증 시스템 구현 (Implementation of FPGA Verification System with Slave FIFO Interface and FX3 USB 3 Bridge Chip)

  • 최병윤
    • 한국정보통신학회논문지
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    • 제25권2호
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    • pp.259-266
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    • 2021
  • USB 버스는 편리하게 사용할 수 있고 빠르게 데이터를 전송하는 장점이 있어서, FPGA 개발보드와 PC 사이의 표준적인 인터페이스이다. 본 논문에서는 Cypress FX3 USB 3 브릿지 칩에 대한 slave FIFO 인터페이스를 사용하여 FPGA 검증 시스템을 구현하였다. slave FIFO 인터페이스 모듈은 FIFO 구조의 호스트 인터페이스 모듈과 마스터 버스 제어기와 명령 해독기로 구성되며, FX3 브릿지 칩에 대한 스트리밍 데이터 통신과 사용자 설계 회로에 대한 메모리 맵 형태의 입출력 인터페이스를 지원한다. 설계 검증 시스템에는 Cypress FX3 칩과 Xilinx Artix FPGA (XC7A35T-1C5G3241) 칩으로 구성된 ZestSC3 보드가 사용되었다. C++ DLL 라이브러리와 비주얼 C# 언어를 사용하여 개발한 GUI 소프트웨어를 사용하여, 사용자 설계 회로에 대한 FPGA 검증 시스템이 다양한 클록 주파수 환경에서 올바로 동작함을 확인하였다. 설계한 FPGA 검증 시스템의 slave FIFO 인터페이스 회로는 모듈화 구조를 갖고 있어서 메모리맵 인터페이스를 갖는 다른 사용자 설계 회로에도 응용이 가능하다.

자바 바이트코드의 검증을 위한 프레임워크 설계 (A Design of Verification Framework for Java Bytecode)

  • 김제민;박준석;유원희
    • 디지털산업정보학회논문지
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    • 제7권2호
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    • pp.29-37
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    • 2011
  • Java bytecode verification is a critical process to guarantee the safety of transmitted Java applet on the web or contemporary embedded devices. We propose a design of framework which enables to analyze and verify java bytecode. The designed framework translates from a java bytecode into the intermediate representation which can specify a properties of program without using an operand stack. Using the framework is able to produce automatically error specifications that could be occurred in a program and express specifications annotated in intermediate representation by a user. Furthermore we design a verification condition generator which converts from an intermediate representation to a verification condition, a verification engine which verifies verification conditions from verification condition generator, and a result reporter which displays results of verification.

Two Verification Phases in Multimedia Authoring Modeling

  • Wijaya, Marvin Chandra;Maksom, Zulisman;Abdullah, Muhammad Haziq Lim
    • Journal of information and communication convergence engineering
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    • 제19권1호
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    • pp.42-47
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    • 2021
  • Multimedia Authoring Tool is a tool for creating multimedia presentations. With this tool, a user can produce playable multimedia documents. A Multimedia Authoring Tool requires input in the form of a spatial layout and a temporal layout. Users can make many mistakes in creating multimedia presentations and verification is required in the Multimedia Authoring process in order to produce multimedia documents. In this study, two verification phases are proposed: Time Computation and Spatiotemporal Conflict Verification. In the experiment conducted for this study, two kinds of verification were carried out: The use of single-phase verification and the use of double-phase verifications. By using these two types of verification, it became easier to successfully detect errors in the spatial and temporal layouts, and the types of verification have also been successful in increasing the success of error detection.

출입문 보안을 위한 블록체인 기반의 출입코드키 검증 서비스 모델 (An Access Code Key for Verification Service Model on the Blockchain in a Door Security)

  • 홍기현;이병문
    • 한국멀티미디어학회논문지
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    • 제25권10호
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    • pp.1416-1432
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    • 2022
  • The access control system is a system that allows users to selectively enter the building by granting an access key to the user for security. Access keys with weak security are easily exposed to attackers and cannot properly perform the role that authenticates users. Access code keys should be protected from forgery or spoofing. For this reason, access key verification service models is important in security. However, most models manage all access keys on one central server. This method not only interrupts all services due to server errors, but also risks forgery and spoofing in the process of transmitting access keys. Therefore, blockchain algorithms are used to reduce this risk. This paper proposes a blockchain-based access key verification service model that used distributed stored blockchain gateways on storing access keys and authenticates the user's identity based on them. To evaluate the performance of this model, an experiment was conducted to confirm the performance of the access key forgery recovery rate and the blockchain network performance. As a result, the proposed method is 100% forgery recovery rate, and the registration and verification process is evaluated at 387.58 TPS and 136.66 TPS.