• Journal of KIISE:Software and Applications
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• v.29 no.1_2
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• pp.80-90
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• 2002

Clustering is a useful technique for grouping data points such that points within a single group/cluster have similar characteristics. Many clustering algorithms have been developed and used in engineering applications including pattern recognition and image processing etc. Recently, it has drawn increasing attention as one of important techniques in data mining. However, clustering algorithms such as K-means and Fuzzy C-means suffer from difficulties. Those are the needs to determine the number of clusters apriori and the clustering results depending on the initial set of clusters which fails to gain desirable results. In this paper, we propose a new clustering algorithm, which solves mentioned problems. In our method we use evolutionary algorithm to solve the local optima problem that clustering converges to an undesirable state starting with an inappropriate set of clusters. We also adopt a new measure that represents how well data are clustered. The measure is determined in terms of both intra-cluster dispersion and inter-cluster separability. Using the measure, in our method the number of clusters is automatically determined as the result of optimization process. And also, we combine heuristic that is problem-specific knowledge with a evolutionary algorithm to speed evolutionary algorithm search. We have experimented our algorithm with several sets of multi-dimensional data and it has been shown that one algorithm outperforms the existing algorithms.

• The KIPS Transactions:PartA
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• v.16A no.2
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• pp.113-124
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• 2009

With increasing multicore system, much effort has been put on the performance improvement of its application. Because multicore system has multiple processing devices in one system, its processing power increases compared to the single core system. However in many cases the advantages of multicore can not be exploited fully because the existing software and hardware were designed to be suitable for single core. When the existing software runs on multicore, its performance improvement is limited by the bottleneck of sharing resources and the inefficient use of cache memory on multicore. Therefore, according as the number of core increases, it doesn't show performance improvement and shows performance drop in the worst case. In this paper we propose a method of performance improvement of multicore system by applying Flow-Level Parallelism to the existing TCP/IP network application and operating system. The proposed method sets up the execution environment so that each core unit operates independently as much as possible in network application, TCP/IP stack on operating system, device driver, and network interface. Moreover it distributes network traffics to each core unit through L2 switch. The proposed method allows to minimize the sharing of application data, data structure, socket, device driver, and network interface between each core. Also it allows to minimize the competition among cores to take resources and increase the hit ratio of cache. We implemented the proposed methods with 8 core system and performed experiment. Experimental results show that network access speed and bandwidth increase linearly according to the number of core.

• The KIPS Transactions:PartA
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• v.8A no.4
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• pp.479-488
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• 2001

As the SoC designs complexity constantly increases, the simulation that uses their software models simply takes too much time. To solve this problem, FPGA-based logic emulators have been developed and commonly used in the industry. However, FPGA-based logic emulators are facing with the problems of which not only very low FPGA resource usage rate due to the very limited number of pins in FPGAs, but also the emulation speed getting slow drastically as the complexity of designs increases. In this paper, we proposed a new innovative emulation architecture and its software that has high FPGA resource usage rate and makes the emulation extremely fast. The proposed emulation system has merits to overcome the FPGA pin limitation by pipelined ring which transfers multiple logic signal through a single physical pin, and it also makes possible to use a high speed system clock through the intelligent ring topology. In this topology, not only all signal transfer channels among EPGAs are totally separated from user logic so that a high speed system clock can be used, but also the depth of combinational paths is kept swallow as much as possible. Both of these are contributed to achieve high speed emulation. For pipelined singnals transfer among FPGAs we adopt a few heuristic scheduling having low computation complexity. Experimental result with a 12 bit microcontroller has shown that high speed emulation possible even with these simple heuristic scheduling algorithms.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.821-830
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• 2001

H.323 proposes to use Mobile IP and H.323 ad hoc conference signaling to provide Handoff function to a mobile terminal. But H.323 ad hoc conference signaling has a drawback. It requires an H.323 endpoint to do a complex conference signaling which makes inter-operability between H.323 endpoints difficult and takes the longer signaling time. In this paper, we propose an Handoff signaling using H.323 rerouting(Third party initiated Pause and Rerouting). H.323 rerouting signaling only requires an H.323 endpoint to do H.323 basic signaling in reestablishing media channel, and makes inter-operability more easier and provides the faster Handoff. To do this, our H.323 GK has derived H.245 control channel using tunneling for all H.323 calls including the fast connect calls which enable endpoints communicate each other if they don\`t have H.245 control channel. In order to evaluate the performance of the proposed signaling, we have conducted an experiment that compares a call transfer signaling using H.323 rerouting with ad hoc conference signaling in inter-operability and signaling delay. The results of our experiment shows that the call transfer signaling can inter-operate with four H.323 endpoints among five H.323 endpoints of other vendors and reduces the signaling delay average 1.4 sec.

• Journal of Korean Society of Transportation
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• v.33 no.6
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• pp.584-597
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• 2015

A considerable amount of literature has been published on pedestrian LOS. So far, however, there is a limitation that LOS analysis methodologies has concentrated on quantitative variables such as pedestrian flow rate, speed and space. This paper intended to suggest the accessibility variable which can not be considered on previous study. The factor was defined and quantified using public transport attributes in particular. This study was carried out in three phases: 1. defined accessibility employing public mode location and service information. 2. investigated the relationship between accessibility and pedestrian flow rate 3. developed the model to establish the factors affected to pedestrian LOS. The results showed that accessibility, walkway attribute and land use type affected the pedestrian LOS. Especially, accessibility and commercial area ratio had negative relationship with LOS. Futhermore, pedestrian LOS declined when obstacle of bus station located on the walkway. On the contrary, LOS was upgraded when sufficient effective width or residential area was secured. These results can receive considerable critical attentions related to determination of pedestrian LOS or effective walkway width.

• Weed & Turfgrass Science
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• v.1 no.4
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• pp.6-12
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• 2012

A fact-finding survey was conducted to obtain the basic information on nation-wide weed distribution and farmer's opinions to weed control strategy in paddy field. Most respondents considered Echinochloa spp., Monochloa vaginalis, Sagittaria trifolia, and Scirpus juncoides etc. as dominate weeds in paddy fields. And herbicide resistant weed species were M. vaginalis, S. juncoides, E. oryzicola and S. pygmaea etc. Purchase guidances for herbicide selection, experience of farmers was 34.0% and dealers recommendation was 33.9% at farmer's level. And paddy field herbicides application frequence were one time 15.6% but twice 75.6%. Preferred herbicides were ranked in the following order: oxadizone 12% EC, butachlor 5% GR, butachlor 33% CS, mefenacet pyrazodulfuron-ethyl 21.42% SC, and oxadiargyl 1.7% EC etc. in paddy fields. And in most preferred foliar herbicide were bentazone MCPA 38.6% SL and bentazone cyhalop-butyl 18.5% ME, 48.5% and 22.3%, respectively.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.9
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• pp.2516-2522
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• 2009

The data which analyze the results of blood cultures are crucial basic information of the empirical therapy for patients with infection since the patterns of the species of microorganism isolated from blood and the results of antibiotic susceptibility test vary depending upon patients general features. Especially, in case of ESBL-producing bacteria, there is a close relation with use of antibiotics. Therefore, we carried out the research with the results of blood culture and antibiotic. 1. Total 39,305 cases of blood culture samples were investigated and positive patients of 2,216 (20.0%) were found. Among those, there were 40 patients with ESBL positive, and blood culture positive samples were 4,798 (12.2%). ESBL positive bacteria were found in 86 samples (including double checked culture bacteria). 2. The majority of ESBL producing bacteria were E. coli, K. pneumoniae and K. oxitoca as ordering based on the number. 3. The research showed the results that there were more females than male with the bacterias, more E. coli in over 50 years old aged group than other bacterias, more K. pneumoniae and K.oxitoca in less 1 year old aged group than other bacterias and largest numbers of patients with 13 patients (32.5%) in Chungcheongnam-do province were found. 4. The most common ESBL producing bacteria were E. coli throughout 3 years, but K, pneumoniae and K. oxitoca were also fairly found. Interestingly, E. coli was highly found in over 50 years old patients.

• Journal of Korea Multimedia Society
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• v.14 no.4
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• pp.529-537
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• 2011

In this paper, we propose a stable scale adaptive tracking method that uses centroids of the target colors. Most scale adaptive tracking methods have utilized histograms to determine target window sizes. However, in certain cases, histograms fail to provide good estimates of target sizes, for example, in the case of occlusion or the appearance of colors in the background that are similar to the target colors. This is due to the fact that histograms are related to the numbers of pixels that correspond to the target colors. Therefore, we propose the use of centroids that correspond to the target colors in the scale adaptation algorithm, since centroids are less sensitive to changes in the number of pixels that correspond to the target colors. Due to the spatial information inherent in centroids, a direct relationship can be established between centroids and the scale of target regions. Generally, after the zooming factors that correspond to all the target colors are calculated, the unreliable zooming factors are filtered out to produce a reliable zooming factor that determines the new scale of the target. Combined with the centroid based tracking algorithm, the proposed scale adaptation method results in a stable scale adaptive tracking algorithm. It tracks objects in a stable way, even when the background colors are similar to the colors of the object.

• Journal of KIISE:Computing Practices and Letters
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• v.7 no.4
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• pp.372-381
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• 2001

In this paper SEED, the Korea Standard 128-bit block cipher algorithm is implemented with VHDL and mapped into one FPGA. SEED consists of round key generation block, F function block, G function block, round processing block, control block and I/O block. The designed SEED is realized in an FPGA but we design it technology-independently so that ASIC or core-based implementation is possible. SEED requires many hardware resources which may be impossible to realize in one FPGA. So it is necessary to minimize hardware resources. In this paper only one G function is implemented and is used for both the F function block and the round key block. That is, by using one G function sequentially, we can realize all the SEED components in one FPGA. The used cell rate after synthesis is 80% in Altem FLEXI0KlOO. The resulted design has 28Mhz clock speed and 14.9Mbps performance. The SEED hardware is technology-independent and no other external component is needed. Thus, it can be applied to other SEED implementations and cipher systems which use SEED.

• Journal of KIISE:Software and Applications
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• v.32 no.7
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• pp.683-692
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• 2005

Java specification states that all accesses to an object must be checked at runtime if object refers to null. Since Java is an object-oriented language, object accesses are frequent enough to make null pointer checks affect the performance significantly. In order to reduce the performance degradation, there have been attempts to remove redundant null pointer checks. For example, in a Java environment where a just-in-time (JIT) compiler is used, the JIT compiler removes redundant null pointer check code via code analysis. This paper proposes a technique to remove additional null pointer check code that could not be removed by previous JIT compilation techniques, via early null pointer check using an architectural feature called predication. Generally, null point check code consists of two instructions: a compare and a branch. Our idea is moving the compare instruction that is usually located just before an use of an object, to the point right after the object is defined so that the total number of compare instructions is reduced. This results in reduction of dynamic and static compare instructions by 3.21$\%$ and 1.98$\%$. respectively, in SPECjvm98 bechmarks, compared to the code that has already been optimized by previous null pointer check elimination techniques. Its performance impact on an Itanium machine is an improvement of 0.32$\%$.