• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.3
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• pp.121-127
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• 2012

An integrated crypto engine for encryption and decryption of AES algorithm based on unified data-path architecture is efficiently designed and implemented in this paper. In order to unify the design of encryption and decryption, internal steps in single round is adjusted so as to operate with columns after row operation is completed and efficient method for a buffer is developed to simplify the Shift Rows operation. Also, only one S-box is used for both key expansion and crypto operation and Key-Box saving expended key is introduced provide the key required in encryption and decryption. The functional simulation based on ModelSim simulator shows that 164 clocks are required to process the data of 128bits in the proposed engine. In addition, the proposed engine is implemented with 6,801 gates by using Xilinx Synthesizer. This demonstrate that 40% gates savings is achieved in the proposed engine, compared to individual designs of encryption and decryption engine.

• Journal of the Korean Society for Railway
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• v.6 no.1
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• pp.66-72
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• 2003

Railway sign(graphic sign, diagraphics) designs require good recognition with universality to transmit accurate and speedy information as they connect people around the station and other transport systems. An important point of signs is how to design and deliver the contents to the viewers as a communication service tools. It needs to establish design guidelines with standardization and unified system to show their contents and images clearly like common language with visuality, attractivity and generality. These requisites are important for both aesthetics legibility and unified standards to maximize the effectiveness of pictograms for the use of the general public, who require systematic suggestion and management.

• Proceedings of the KSR Conference
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• 2003.05a
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• pp.176-184
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• 2003

Railway sign(graphic sign, diagraphics) designs require good recognition with universality to transmit accurate and speedy information as they connect people around the station and other transport systems. An important point of signs is how to design and deliver the contents to the viewers as a communication service tools. It needs to establish design guidelines with standardization and unified system to show their contents and images clearly like common language with visuality, attractivity and generality. These requisites are important for both aesthetics legibility and unified standards to maximize the effectiveness of pictograms for the use of the general public, who require systematic suggestion and management.

• Proceedings of the Korean Information Science Society Conference
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• 2001.04a
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• pp.583-585
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• 2001

RUP의 Unified Process Model 에는 Use-Case Model, Analysis Model, Design Model, Deployment Model, Implementation Model, Test Model의 6가지 모델이 있다. 이 모델들은 모두 일관성이 있다. 한 모델에서 나오는 요소들은 전, 후 단계에서 다른 모델들과 Trace Dependencies를 갖는다. 예를 들면, Use-Case Model에서는 한 Use Case는 Design Model에서 Use-Case Realization으로 Test Model에서는 Test Case로 Trace Dependencies를 갖는다. 소프트웨어 개발에서 추적성은 Understandability와 Change Propagation 과 같은 이유로 매우 중요하다. 그러나 RUP에서는 각 모델들간의 추적성에 대한 지침이 충분히 제시되어 있지 않아, 개발 과정중에 요구사항의 변경이나 에러 수정 또는 향후 관리 시에 어려움을 겪고 있다. 본 논문에서는 이 점에 중점을 두고 RUP에서 제시하고 있는 모델들 간의 추적성 중 설계모델에서 분석모델로의 추적성 적용지침을 제시한다.

• Annual Conference of KIPS
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• 2003.11c
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• pp.1677-1680
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• 2003

RUP(Rational Unified Process)의 Unified Process Model 에는 Use Case Model, Analysis Model, Design Model, Deployrnent Model, Implementation model, Test Model의 6가지 모델이 있다. 이 모델들은 다음단계의 모델에 대한 일관성 및 의존성을 가진다. 한 모델에서 발생되는 요소들은 전, 후 단계에서 다른 모델들과 Trace Dependencies 를 갖는다. 이러한 의존적인 관계들은 각각의 요소들 사이의 진행, 기록 관계를 나타낸다. 그러나 대부분의 시스템은 이러한 관계 및 의존성 없이 설계되어져 전체적인 일관성을 이루지 못 하였다. 본 논문에서는 이러한 관계를 유지 하면서 사용자의 요구사항에 일관성 있는 Use Case 모델을 설계하고자 한다. 따라서 본 논문에서는 대학 종합정보시스템 구축의 일부분인 구매관리 시스템을 분석하여 컴포넌트 시스템 모델을 제시한다.

• Journal of Power Electronics
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• v.19 no.3
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• pp.815-826
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• 2019

This paper discusses a simple control approach for a Unified Power Conditioner (UPC) system to achieve power quality compensation at the point of common coupling in distribution systems. The proposed Instantaneous Power Estimation Algorithm (IPEA) for shunt and series active power filters uses a simple mathematical concept that reduces the complexity in the design of the controller. The performance of a UPC is verified with a system subjected to voltage distortions, sags/swells and unbalanced loads using MATLAB/SIMULINK. The simulation study shows that a UPC with the proposed control algorithm can effectively compensate for voltage and current harmonics, unbalance and reactive power. The control algorithm is experimentally implemented using dSPACE DS1104 and its effectiveness has been verified.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.12
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• pp.63-69
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• 1999

Center of photon mass, defined as the center of axial photon distribution in each half, is proposed as a unified design parameter in quarter wavelength shifted(QWS) DFB lasers. Shown is the way the parameter is related to the threshold pain difference and uniformity in axial photon density, which determine single-frequency stability of DFB lasers. Also, a general rule for single-frequency DFB laser design is presented. Using the design rule, we propose a sampled grating QWS-DFB laser that has a wider $_KL$ range 0f 100% single-frequency yield.

• Journal of Information Technology Applications and Management
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• v.9 no.1
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• pp.85-96
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• 2002

Nowadays an information exchange on XML such as B2B electronic commerce is spreading. Therefore the systematic and stable management mechanism for storing the exchanged Information is needed. For this goal there are many research activities for connection between XML application and relational database. But because XML data have hierarchical structures and relational database can store only flat-structured data, we need to store XML data in object-oriented database that support hierarchical structure. Accordingly the modeling methodology for storing XML data in object-oriented database is needed. In order to build good quality application systems, modeling is an important first step. In 1997, the OMG adopted the UML as its standard modeling language. Since industry has warmly embraced UML, its popularity should become more important in the future. So a design methodology based on UML is need to develop efficiently XML applications. In this paper, we propose a unified design methodology for XML applications based on object- oriented database using UML. To this goal, first we introduce a XML modeling methodology to design W3C XML schema using UML and second we propose data modeling methodology for object-oriented database schema to store efficiently XML data in object-oriented databases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.661-666
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• 2002

We need the flexible method for communication network configuration and fault management business procedure. Therefore development of systematic integrating fault management system is essential to meet on these requests. We must design the integrating fault management system so that can run the repair processing for both data communication network management and new next generation data communication network of various type. In general it is effective that the system is consisted of decentralized module to be accessibele for business logic and datum to remote area. To Solve these problem, a method is to use object-oriented design technique. That is, it is to abstract reusability objects and make component module using the abstracted objects. In this paper, we propose a fault management system of communication network service using object-oriented design techniques which are UML(Unified Modeling Language) and EJB(Enterprise Java Bean).

• Journal of IKEEE
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• v.19 no.3
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• pp.392-399
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• 2015

This paper proposes a unified $4{\times}4$ transform architecture for HEVC and VP9 codec to reduce hardware size. It performs HEVC $4{\times}4$ IDCT, HEVC $4{\times}4$ IDST, VP9 $4{\times}4$ IDCT, and VP9 $4{\times}4$ IADST in a unified hardware. HEVC $4{\times}4$ IDCT and VP9 $4{\times}4$ IDCT have same IDCT computation except for the scales of coefficients. Similarly, HEVC $4{\times}4$ IDST and VP9 $4{\times}4$ IADST have same IDST computation except for the scales of coefficients. Furthermore, IDCT and IDST have quite a lot of similarity, so they can share some hardwares in common. So the proposed hardware performs all 4 operations in a unified hardware, where each operation has its own multiplication coefficients with shared butterfly adders. The synthesized block in 0.18 um technology is 6,679 gates, and the gate count is reduced by 25.3% in comparison with conventional designs.