• Title/Summary/Keyword: ultrahigh vacuum chemical vapor deposition

Search Result 12, Processing Time 0.022 seconds

Low-Temperature Si and SiGe Epitaxial Growth by Ultrahigh Vacuum Electron Cyclotron Resonance Chemical Vapor Deposition (UHV-ECRCVD)

  • Hwang, Ki-Hyun;Joo, Sung-Jae;Park, Jin-Won;Euijoon Yoon;Hwang, Seok-Hee;Whang, Ki-Woong;Park, Young-June
    • Proceedings of the Korea Association of Crystal Growth Conference
    • /
    • 1996.06a
    • /
    • pp.422-448
    • /
    • 1996
  • Low-temperature epitaxial growth of Si and SiGe layers of Si is one of the important processes for the fabrication of the high-speed Si-based heterostructure devices such as heterojunction bipolar transistors. Low-temperature growth ensures the abrupt compositional and doping concentration profiles for future novel devices. Especially in SiGe epitaxy, low-temperature growth is a prerequisite for two-dimensional growth mode for the growth of thin, uniform layers. UHV-ECRCVD is a new growth technique for Si and SiGe epilayers and it is possible to grow epilayers at even lower temperatures than conventional CVD's. SiH and GeH and dopant gases are dissociated by an ECR plasma in an ultrahigh vacuum growth chamber. In situ hydrogen plasma cleaning of the Si native oxide before the epitaxial growth is successfully developed in UHV-ECRCVD. Structural quality of the epilayers are examined by reflection high energy electron diffraction, transmission electron microscopy, Nomarski microscope and atomic force microscope. Device-quality Si and SiGe epilayers are successfully grown at temperatures lower than 600℃ after proper optimization of process parameters such as temperature, total pressure, partial pressures of input gases, plasma power, and substrate dc bias. Dopant incorporation and activation for B in Si and SiGe are studied by secondary ion mass spectrometry and spreading resistance profilometry. Silicon p-n homojunction diodes are fabricated from in situ doped Si layers. I-V characteristics of the diodes shows that the ideality factor is 1.2, implying that the low-temperature silicon epilayers grown by UHV-ECRCVD is truly of device-quality.

  • PDF

SiGe Nanostructure Fabrication Using Selective Epitaxial Growth and Self-Assembled Nanotemplates

  • Park, Sang-Joon;Lee, Heung-Soon;Hwang, In-Chan;Son, Jong-Yeog;Kim, Hyung-Jun
    • Proceedings of the Materials Research Society of Korea Conference
    • /
    • 2009.05a
    • /
    • pp.24.2-24.2
    • /
    • 2009
  • Nanostuctures such as nanodot and nanowire have been extensively studied as building blocks for nanoscale devices. However, the direct growth of the nanostuctures at the desired position is one of the most important requirements for realization of the practical devices with high integrity. Self-assembled nanotemplate is one of viable methods to produce highly-ordered nanostructures because it exhibits the highly ordered nanometer-sized pattern without resorting to lithography techniques. And selective epitaxial growth (SEG) can be a proper method for nanostructure fabrication because selective growth on the patterned openings obtained from nanotemplate can be a proper direction to achieve high level of control and reproducibility of nanostructucture fabrication. Especially, SiGe has led to the development of semiconductor devices in which the band structure is varied by the composition and strain distribution, and nanostructures of SiGe has represented new class of devices such nanowire metal-oxide-semiconductor field-effect transistors and photovoltaics. So, in this study, various shaped SiGe nanostructures were selectively grown on Si substrate through ultrahigh vacuum chemical vapor deposition (UHV-CVD) of SiGe on the hexagonally arranged Si openings obtained using nanotemplates. We adopted two types of nanotemplates in this study; anodic aluminum oxide (AAO) and diblock copolymer of PS-b-PMMA. Well ordered and various shaped nanostructure of SiGe, nanodots and nanowire, were fabricated on Si openings by combining SEG of SiGe to self-assembled nanotemplates. Nanostructure fabrication method adopted in this study will open up the easy way to produce the integrated nanoelectronic device arrays using the well ordered nano-building blocks obtained from the combination of SEG and self-assembled nanotemplates.

  • PDF