• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.141-141
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• 1999

전기화학과 초고진공(ultra-high vacuum, UHV) 분광법을 이용하여 고체/액체의 계면에서 일어나는 현상을 분자단위에서 이해하고 조절하기 위한 연구를 수행하였다. 이들 중 전기화학으로 형성된 구리 및 은 금속(sub)monlayer 박막을 그 예로 선택하여 소개한다. 초박막 금속의 흡착량은 cyclic voltammogram과 새로 개발된 Auger electron spectroscopy (AES) 정량법을 통해 얻어졌고, 이 값들은 low energy electron diffraction (LEED) 및 in-situ atomic force microscopy (AFM)법을 이용한 구조 분석결과와 비교되어졌다. 또한 화학상태를 확인하기 위하여 core-level electron energyy loss spectroscopy (CEELS)를 사용하였다. 먼저 황산 전해질에서 금(111) 단결정 전극상에 전기화학적으로 형성된 굴의 계면특성을 조사하였다. 특정 전위값에서 2/3 ML의 구리와 1/3 ML의 음이온이 상호 흡착하여 ({{{{ SQRT { 3} }}$\times${{{{ SQRT { 3} }}) 격자 구조를 보였고, 전위값이 커지거나 줄어들면, 이 구조가 사라지는 현상이 관찰되었다. 즉 이 ({{{{ SQRT { 3} }}}}$\times${{{{ SQRT { 3} }}}}) 흡착구조는 첫 번째 UPD underpotential deposition) 피크에 특이하게 관련되어 있음을 알 수 있었다. 금속 초박막 형성에 미치는 음이온의 영향을 좀 더 확인하기 위해 초박막 은이 증착된 금 단결정 전극상의 황산 음이온에 관하여 연구하였다. 은의 증착이 일어날 수 없는 양전위값 영역에서 ({{{{ SQRT { 3} }}}}$\times${{{{ SQRT { 3} }}}})의 규칙적인 음이온의 구조를 보였다. 그리고 은의 장착은 세척 과정과 용액의 농도에 따라 p(3$\times$3)과 p(5$\times$5)의 규칙적인 두가지 구조를 가졌다. in-situ AFM에서는 p(3$\times$3)의 은 증착 구조만 나타났고, 음 전위값으로 옮겨가면 p(1$\times$1) 구조로 바뀌었다. ex-situ 초고진공 결과와 이 AFM의 in-situ 결과를 상호 비교 논의할 것이다. 음이온의 흡착이 없는 묽은 플로르산(HF) 전해질에서 은은 전위값을 음전위 쪽으로 이동해 감에 따라 p(3$\times$3), p(5$\times$5), (5$\times$5), (6$\times$6), 그리고 (1$\times$1)의 연속적 구조 변화를 보였다. 이 다양한 구조들을 AES로부터 얻어진 표면 흡착량과 연결시켰더니 정량적으로 잘 일치되는 결과를 보였다. 전기화학적인 증착에서는 기존의 진공 증착과 비교할 때 음이온의 공흡착이 금속 초박막 형성 메카니즘에 큰 영향을 미침을 알 수 있었다. 또한 은의 전기화학적 다층박막 성장은 MSM (monolayer-simultaneous-multilayer) 메카니즘을 따름을 확인하였다. 마지막으로 구조 및 양이 규칙적으로 조절되는 전극의 응용가능성이 간단히 논의될 것이다.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.279-279
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• 2011

나노 입자를 이용한 비휘발성 메모리 소자의 전기적 특성 향상을 위하여 일함수가 Si 보다 큰 금속, 금속산화물, 금속 실리사이드 나노입자를 이용한 다양한 형태의 메모리 구조가 제안되어져 왔다.[1] 특히 이와 같은 나노 부유 게이트 구조에서 터널 절연막의 구조를 소자의 동작 속도를 결정하는데 이는 터널링 되어 주입되는 전자의 확률에 의존하기 때문이다. 양자 우물에 국한된 전하가 누설되지 않으면서 주입되는 전자의 터널링 확률을 증가시키기 위하여, dielectric constant 와 barrier height를 고려한 다양한 구조의 터널 절연막의 형태가 제안 되었다.[2-3] 특히 낮은 전계에서도 높은 터널링 확률은 메모리 소자의 동작 속도를 향상시킬 수 있다. 본 연구에서는 n형 Si 기판위에 Si3N4 및 HfAlO를 각각 1.5 nm 및 3 nm 로 atomic layer deposition 방법으로 증착하였으며 3~5 nm 지름을 가지는 $TiSi_2$ 및 $WSi_2$ 나노 입자를 형성한 후 컨트롤 절연막인 $SiO_2$를 ultra-high vacuum sputtering을 사용하여 20 nm 두께로 형성 하였다. 마지막으로 $200{\mu}m$ 지름을 가지는 Al 전극을 200 nm 두께로 형성하여 나노 부유 게이트 커패시터를 제작하였다. 제작된 소자는 Agilent E4980A precision LCR meter 및 HP 4156A precision semiconductor parameter analyzer 를 사용하여 전기용량-전압 및 전류-전압 특성분석을 하여 전하저장 특성 및 제작된 소자의 터널링 특성을 확인 하여 본 연구를 통하여 제작된 나노 부유 게이트 커패시터 구조가 메모리 소자응용이 가능함을 확인하였다.

• Journal of the Korean Society for Railway
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• v.14 no.2
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• pp.143-150
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• 2011

This paper presents a preliminary study for air-tightness evaluation of vacuum tube structures for super-speed tube railway systems. The formula for flow rate of the air caused by the pressure difference of the inside and outside of the tube structure is derived based on Darcy's law. A test is then performed to measure the air-permeability of concrete with various compressive strengths, the result of which is used for analytical simulation of the air intrusion for a tube structure with a preliminarily defined section. It has been shown that concrete with the compressive strength of at least more than 50MPa is recommended for effective operation and maintenance of the vacuum pump systems, as the air-permeability of concrete is inversely proportional to the exponent of its compressive strength.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.290.1-290.1
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• 2013

The electrical characterization of Au islands on TiO2 at nanometer scale (as a Schottky nanodiode) has been studied with conductive atomic force microscopy in ultra-high vacuum. The diverse sizes of the Au islands were formed by using self-assembled patterns on n-type TiO2 semiconductor film using the Langmuir-Blodgett process. Local conductance images showing the current flowing through the TiN coated AFM probe to the surface of the Au islands on TiO2 was simultaneously obtained with topography, while a positive sample bias is applied. The boundary of the Au islands revealed a higher current flow than that of the inner Au islands in current AFM images, with the forward bias presumably due to the surface plasmon resonance. The nanoscale Schottky barrier height of the Au/TiO2 Schottky nanodiode was obtained by fitting the I-V curve to the thermionic emission equation. The local resistance of the Au/TiO2 nanodiode appeared to be higher at the larger Au islands than at the smaller islands. The results suggest that conductive atomic force microscopy can be used to reveal the I-V characterization of metal size dependence and the electrical effects of surface plasmon on a metal-semiconductor Schottky diode at nanometer scale.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.128.1-128.1
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• 2013

We investigated the correlation between electrical transport and mechanical stress in $Bi_2Te_2Se$ by using a conductive probe atomic force microscopy in an ultra-high vacuum environment. Uniform distribution of measured friction and current were observed over a single quintuple layer terrace, which is an indication of the uniform chemical composition of the surface. By measuring the charge transport of $Bi_2Te_2Se$ surface as a function of the load applied by a tip to the sample, we found that the current density varies with applied load. The variation of current density was explained in light of the combined effect of the changes in the in-plane conductance and spin-orbit coupling that were theoretically predicted. We suppose that the local density of states is modified by tip-induced strain, but topological phase still remains. We exposed a clean topological insulator surface by tip-induced indentation. The surface conductance on the indented $Bi_2Te_2Se$ surface was studied, and the role of surface oxide on the surface conductance is discussed.

• Korean Journal of Materials Research
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• v.29 no.4
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• pp.241-251
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• 2019

There are several manufacturing techniques for developing thermionic cathodes for vacuum ultraviolet(VUV) ionizers. The triple alkaline earth metal emitters(Ca-Sr-Ba) are formulated as efficient and reliable thermo-electron sources with a great many different compositions for the ionizing devices. We prepare two basic suspensions with different compositions: calcium, strontium and barium. After evaluating the electron-emitting performance for europium, gadolinium, and yttrium-based cathodes mixed with these suspensions, we selected the yttrium for its better performance. Next, another transition metal indium and a lanthanide metal neodymium salt is introduced to two base emitters. These final composite metal emitters are coated on the tungsten filament and then activated to the oxide cathodes by an intentionally programmed calcination process under an ultra-high vacuum(${\sim}10^{-6}torr$). The performance of electron emission of the cathodes is characterized by their anode currents with respect to the addition of each element, In and Nd, and their concentration of cathodes. Compared to both the base cathodes, the electron emission performance of the cathodes containing indium and neodymium decreases. The anode current of the Nd cathode is more markedly degraded than that with In.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.61.1-61.1
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• 2015

Nanoscale semiconductor plasma processing has become one of the most challenging issues due to the limits of physicochemical fabrication routes with its inherent complexity. The mission of future and emerging plasma processing for development of next generation semiconductor processing is to achieve the ideal nanostructures without abnormal profiles and damages, such as 3D NAND cell array with ultra-high aspect ratio, cylinder capacitors, shallow trench isolation, and 3D logic devices. In spite of significant contributions of research frontiers, these processes are still unveiled due to their inherent complexity of physicochemical behaviors, and gaps in academic research prevent their predictable simulation. To overcome these issues, a Korean plasma consortium began in 2009 with the principal aim to develop a realistic and ultrafast 3D topography simulator of semiconductor plasma processing coupled with zero-D bulk plasma models. In this work, aspects of this computational tool are introduced. The simulator was composed of a multiple 3D level-set based moving algorithm, zero-D bulk plasma module including pulsed plasma processing, a 3D ballistic transport module, and a surface reaction module. The main rate coefficients in bulk and surface reaction models were extracted by molecular simulations or fitting experimental data from several diagnostic tools in an inductively coupled fluorocarbon plasma system. Furthermore, it is well known that realistic ballistic transport is a simulation bottleneck due to the brute-force computation required. In this work, effective parallel computing using graphics processing units was applied to improve the computational performance drastically, so that computer-aided design of these processes is possible due to drastically reduced computational time. Finally, it is demonstrated that 3D feature profile simulations coupled with bulk plasma models can lead to better understanding of abnormal behaviors, such as necking, bowing, etch stops and twisting during high aspect ratio contact hole etch.

• Journal of the Korean Magnetics Society
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• v.25 no.2
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• pp.43-46
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• 2015

$Si(100){\backslash}200nm$ $SiO_2{\backslash}5nm$ $Ta{\backslash}5nm$ $MgO{\backslash}35nm$ $Fe_3O_4$ multi-layers were prepared by using RF-sputtering and ultra-high vacuum molecular beam epitaxy (UHV-MBE) techniques. After post-annealing the multi-layers at $500^{\circ}C$ for 1 hour under the high vacuum of ${\sim}1{\times}10^{-6}Torr$, we observed ferromagnetic properties at room temperature as well as the Verwey transition which is the typical features of magnetite crystals formed. We have carried out a comparative study of the effect of Ta buffered layer on the crystallinity and magnetic properties of $Fe_3O_4$ thin films prepared under different growth and annealing conditions.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.178-178
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• 2010

With the scaling down of ULSI(Ultra Large Scale Integration) circuit of CMOS(Complementary Metal Oxide Semiconductor)based electronic devices, the electronic devices become more faster and smaller size that are promising field of semiconductor market. However, very narrow line width has some disadvantages. For example, because of narrow line width, deposition of conformal and thin barrier is difficult. Besides, proportion of barrier width is large, thus resistance is high. Conventional PVD(Physical Vapor Deposition) thin films are not able to gain a good quality and conformal layer. Hence, in order to get over these side effects, deposition of thin layer used of ALD(Atomic Layer Deposition) is important factor. Furthermore, it is essential that copper atomic diffusion into dielectric layer such as silicon oxide and hafnium oxide. If copper line is not surrounded by diffusion barrier, it cause the leakage current and devices degradation. There are some possible methods for improving the these secondary effects. In this study, TaNx, is used of Tertiarybutylimido tris (ethylamethlamino) tantalum (TBITEMAT), was deposited on the 24nm sized trench silicon oxide/silicon bi-layer substrate with good step coverage and high quality film using plasma enhanced atomic layer deposition (PEALD). And then copper was deposited on TaNx barrier using same deposition method. The thickness of TaNx was 4~5 nm. TaNx film was deposited the condition of under $300^{\circ}C$ and copper deposition temperature was under $120^{\circ}C$, and feeding time of TaNx and copper were 5 seconds and 5 seconds, relatively. Purge time of TaNx and copper films were 10 seconds and 6 seconds, relatively. XRD, TEM, AFM, I-V measurement(for testing leakage current and stability) were used to analyze this work. With this work, thin barrier layer(4~5nm) with deposited PEALD has good step coverage and good thermal stability. So the barrier properties of PEALD TaNx film are desirable for copper interconnection.