• Transactions of the Korean Society of Mechanical Engineers A
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• v.23 no.7 s.166
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• pp.1129-1138
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• 1999

[$Moir\acute{e}$] technique is now being extensively investigated as a fast non-contact means of three-dimensional profile measurement especially for reverse engineering. One problem with $moir\acute{e}$ technique is so called $2\pi$-ambiguity problem that limits the maximum step height difference between two neighboring sampling points to be less than half the equivalent wavelength of $moir\acute{e}$ fringes. In this investigation, a new two-wavelength scheme of projection $moir\acute{e}$ topography is proposed and tested to cope with the $2\pi$-ambiguity problem. Experimental results are discussed to assess the new method in measuring large objects with high step discontinuities.

• The Transactions of the Korean Institute of Power Electronics
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• v.13 no.3
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• pp.179-185
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• 2008

In this paper, an advanced torque control scheme of SRM using DITC(Direct Instantaneous Torque Control) and PWM(pulse width modulation) is presented. Different from conventional DITC method, proposed method uses one or two switching modes at every sampling time, instead of only one switching mode. The duty ratio of the phase switch is regulated according to the torque error and simple control rules of DITC. Moreover the sampling time of control can be extended, which allows implementation on low cost micro-controllers. A simple calculation of PWM can assure a constant switching frequency with an excellent control performance. The proposed control method is verified by the simulations and experimental results.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.5
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• pp.67-74
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• 1997

In this paper, we psresent a new scheme to synthetically generate a HPO digital hologram for a three-dimensional image that is modelled as the horizontally stacked two-dimensional images. The proposed method transforms a lightwave field into the angular spectrum of planewaves, which enables this method to use FFT routines, rather than using numerous arithmetic calculations. Hence, this method may be able to not only lead to the dramatically less computation but provide relatively excellent performances due to the phase error-free transformation. We present sampling constraints and implementaton procedure to obtian a hololine for each image and also point out the necessity of interpolation. Simulatioj results are presented to show the comparison with the conventional method in terms of computation time and performances, including the behaviors resulting form the different selection of parameter values to be used in the interpolations.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.15 no.6
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• pp.65-72
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• 2001

This paper deals with a novel full digital control of the single-phase PWM(Pulse Width Modulation) inviter for UPS(Uninterruptible Power Supp1y). The voltage and current of output filter capacitor as a state variable are the feedback control input. In the proposed scheme a double deadbeat control consisting of minor current control loop and major voltage control loop have been developed In addition, a second order deadbeat currents control which should be exactly equal to its reference in two sampling time without error and overshoot is proposed to remove the influence of the calculation time delay. The load current prediction is achieved to compensate the load disturbance. The simulation and experimental result shows that the proposed system offers an output voltage with THD(Total Harmonic Distortion) less than 5% at a full nonlinear load.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.5
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• pp.62-70
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• 2007

In this paper, the boost Power Factor Correction(PFC) technique for Direct Torque Control(DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors(DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC or BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.