• ETRI Journal
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• v.26 no.6
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• pp.615-621
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• 2004

Next generation mobile communication system, such as IMT-2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block-wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit-error rate (BER) performance of the block-wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block-wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.1
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• pp.81-88
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• 2004

Turbo code has been adopted in the 3GPP standard, since its performance is very close to the Shannon limit. However, the turbo decoder requires a lot of computations and the amount of the memory increases as the block size of turbo codes becomes larger. In order to reduce the complexity of the turbo decoder, the Log-MAP, the Max-Log-MAP and the sliding window algorithm have been proposed. In this paper, the performance of turbo codes adopted in the 3GPP standard is analyzed by using the floating point and the fixed point implementation. The efficient decoding method is also proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1387-1395
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• 2004

Turbo decoder inherently requires large memory and intensive hardware complexity due to iterative decoding, despite of excellent decoding efficiency. To decrease the memory space and reduce hardware complexity, various design issues have to be discussed. In this paper, various design issues on Turbo decoder are investigated and the tradeoffs between the hardware complexity and the performance are analyzed. Through the various simulations on the fixed-length analysis, we decided 5-bits for the received data, 6-bits for a priori information, and 7-bits for the quantization state metric, so the performance gets close to that of infinite precision. The MAX operation which is the main function of Log-MAP decoding algorithm is analyzed and the error correction term for MAX* operation can be efficiently implemented with very small hardware overhead. The size of the sliding window was decided as 32 to reduce the state metric memory space and to achieve an acceptable BER.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1052-1061
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• 2003

This paper proposes a novel normalization scheme in the state metric calculation unit for the Block-wise MAP Turbo decoder. The proposed scheme subtracts one of four metrics from the state metrics in a trellis stage and shifts, if necessary, those metrics for normalization. The proposed architecture can reduce power consumption and memory requirement by reducing the number of the state metrics by one in a trellis stage in the Block-wise MAP decoder which requires an intensive state metric calculations. Simulation results show that dynamic power has been reduced by 17.9% and area has been reduced by 6.6% in the Turbo decoder employing the proposed normalization scheme, when compared to the conventional Block-wise MAP Turbo decoders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2C
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• pp.25-30
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• 2005

Turbo code is popularly used for the reliable communication in the presence of burst errors. Even if it shows good error performance near to the Shannon limits, it requires a large amount of memories and exhibits long latency. This paper proposes an architecture for the low power implementation of the Turbo decoder adopting the Max-Log-Map algorithm. In the proposed design, two SISO decoders are designed to operate in parallel, and a novel interleaver is designed to prevent the collision of memory accesses by two SISO decoders. Experimental results show that power consumption has been reduced by about 40% in the proposed decoder compared to previous Turbo decoders. The area overhead due to the additional interleaver controller is negligible.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.5 no.3
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• pp.169-173
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• 2012

This paper investigates the performance of Turbo equalization in wireless multipath channels. Turbo equalization mainly consists of a SISO(soft-in soft-out) equalizer and a SISO decoder. Iterative channel estimators can improve the accuracy of channel estimates by soft information fed back from the SISO decoder. Comparing iterative channel estimators with LMS(least mean square) and RLS(recursive least squares) algorithms, which are the most common algorithms to estimate and track a time-varying channel impulse response, the iterative channel estimator with RLS converges more faster than the one with LMS. However, the difference of BER(bit error rate) performances gradually decreases as the number of iterations for Turbo equalization increases.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.8
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• pp.1854-1863
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• 2003

In the recent digital communication systems, the performance of Turbo Code using the mr correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the huh decoder. However, performance depends on the interleaver depth that needs many delays over the reception process. Moreover, turbo code has been blown as the robust coding methods with the confidence over the fading channel. International Telecommunication Union(ITU) has recently adopted it as the standardization of the channel coding over the third generation mobile communications(IMT­2000). Therefore, in this paper, we preposed the interleaver that has the better performance than existing block interleaver, and modified turbo decoder that has the parallel concatenated structure using MAP algorithm. In the real­time voice and video service over third generation mobile communications, the performance of the proposed two methods was analyzed and compared with the existing methods by computer simulation in terms of reduced decoding delay using the variable decoding method over AWGN and fading channels for CDMA environments.

• Journal of Korea Society of Digital Industry and Information Management
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• v.14 no.4
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• pp.79-85
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• 2018

This paper presents an implementation method of Long Term Evolution-Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a general-purpose multicore Digital Signal Processor (DSP), TMS320C6670. Although the DSP provides some useful coprocessors such as turbo decoder, fast Fourier transformer, Viterbi Coprocessor, Bit Rate Coprocessor etc., it is specific to the base station platform implementation not the mobile terminal platform implementation. This paper shows an implementation method of the LTE-A PDSCH decoder using programmable DSP cores as well as the coprocessors of Fast Fourier Transformer and turbo decoder. First, it uses the coprocessor supported by the TMS320C6670, which can be used for PDSCH implementation. Second, we propose a core programming method using DSP optimization method for block diagram of PDSCH that can not use coprocessor. Through the implementation, we have verified a real-time decoding feasibility for the LTE-A downlink physical channel using test vectors which have been generated from LTE-A Reference Measurement Channel (RMC) Waveform R.6.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.2
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• pp.385-391
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• 2007

In this paper, we propose and observe the Adaptive Modulation system with optimal Turbo Coded V-BLAST (Vertical-Bell-lab Layered Space-Time) technique that is applied the extrinsic information from MAP (Maximum A Posteriori) Decoder with Iterative Decoding to use as a priori probability in two decoding procedures of V-BLAST: ordering and slicing. Also, comparing with the Adaptive Modulation system using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme, we observe how much throughput performance has been improved. As a result of simulation, in the Adaptive Modulation systems with several Turbo Coded V-BLAST techniques, the optimal Turbo Coded V-BLAST technique has higher throughput gain than the conventional Turbo Coded V-BLAST technique. Especially, the results show that the proposed scheme achieves the gain of 1.5 dB SNR compared to the conventional system at 2.5 Mbps throughput.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.273-276
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• 2001

In this thesis we propose symbol-based decoding for turbo codes which is used SOVA as a decoding algorithm. The proposed turbo codes that is interleaved on symbol-by-symbol basis and inputted as n-bit symbols to the decoder. This method makes that the stages of the original trellis are merged together and the trellis depth is reduced by 1/n. We research turbo codes with symbol size n=2 in this paper and its performance.