• 제목/요약/키워드: tunneling field-effect transistor (TFET)

검색결과 33건 처리시간 0.019초

Investigation of InAs/InGaAs/InP Heterojunction Tunneling Field-Effect Transistors

  • Eun, Hye Rim;Woo, Sung Yun;Lee, Hwan Gi;Yoon, Young Jun;Seo, Jae Hwa;Lee, Jung-Hee;Kim, Jungjoon;Kang, In Man
    • Journal of Electrical Engineering and Technology
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    • 제9권5호
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    • pp.1654-1659
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    • 2014
  • Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current ($I_{off}$) and small subthreshold swing (S). However, low on-current ($I_{on}$) of silicon-based TFETs has been pointed out as a drawback. To improve $I_{on}$ of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction structure is proposed and investigated. Its performances have been evaluated with the gallium (Ga) composition (x) for $In_{1-x}Ga_xAs$ in the channel region. According to the simulation results for $I_{on}$, $I_{off}$, S, and on/off current ratio ($I_{on}/I_{off}$), the device adopting $In_{0.53}Ga_{0.47}As$ channel showed the optimum direct-current (DC) performance, as a result of controlling the Ga fraction. By introducing an n-type InGaAs thin layer near the source end, improved DC characteristics and radio-frequency (RF) performances were obtained due to boosted band-to-band (BTB) tunneling efficiency.

Quantum Simulation Study on Performance Optimization of GaSb/InAs nanowire Tunneling FET

  • Hur, Ji-Hyun;Jeon, Sanghun
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제16권5호
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    • pp.630-634
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    • 2016
  • We report the computer aided design results for a GaSb/InAs broken-gap gate all around nanowire tunneling FET (TFET). In designing, the semi-empirical tight-binding (TB) method using $sp3d5s^*$ is used as band structure model to produce the bulk properties. The calculated band structure is cooperated with open boundary conditions (OBCs) and a three-dimensional $Schr{\ddot{o}}dinger$-Poisson solver to execute quantum transport simulators. We find an device configuration for the operation voltage of 0.3 V which exhibit desired low sub-threshold swing (< 60 mV/dec) by adopting receded gate configuration while maintaining the high current characteristic ($I_{ON}$ > $100 {\mu}A/{\mu}m$) that broken-gap TFETs normally have.

포인트 터널링과 라인 터널링을 모두 고려한 실리콘 기반의 포켓 터널링 전계효과 트랜지스터의 최적 구조 조건 (Guide Lines for Optimal Structure of Silicon-based Pocket Tunnel Field Effect Transistor Considering Point and Line Tunneling)

  • 안태준;유윤섭
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2016년도 추계학술대회
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    • pp.167-169
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    • 2016
  • 이 논문은 라인 터널링과 포인트 터널링을 모두 고려한 포켓 터널링 전계효과 트랜지스터의 여러가지 구조 및 물질 파라미터에 따른 시뮬레이션 결과를 소개한다. 포켓의 도핑 농도와 두께가 증가할수록 구동전류 $I_{on}$이 증가하고 포켓의 두께와 게이트 절연체의 유전율이 증가할수록 SS(subthreshold swing)가 좋아짐을 보인다. hump 효과는 SS를 나쁘게 하기 때문에 최소화할 수 있도록 최적의 구조를 만들어야 한다.

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